[SPARC] Prevent meta instructions from being inserted into delay slot… · llvm/llvm-project@6e687cb (original) (raw)

`@@ -184,4 +184,29 @@ entry:

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`ret i32 %2

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`}

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define i32 @test_generic_inst(i32 %arg) #0 {

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;CHECK-LABEL: test_generic_inst:

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;CHECK: ! fake_use: {{.*}}

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;CHECK: bne {{.*}}

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;CHECK-NEXT: nop

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%bar1 = call i32 @bar(i32 %arg)

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%even = and i32 %bar1, 1

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%cmp = icmp eq i32 %even, 0

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; This shouldn't get reordered into a delay slot

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call void (...) @llvm.fake.use(i32 %arg)

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br i1 %cmp, label %true, label %false

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true:

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%bar2 = call i32 @bar(i32 %bar1)

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br label %cont

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false:

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%inc = add nsw i32 %bar1, 1

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br label %cont

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cont:

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%ret = phi i32 [ %bar2, %true ], [ %inc, %false ]

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ret i32 %ret

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}

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declare void @llvm.fake.use(...)

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`attributes #0 = { nounwind "disable-tail-calls"="true" }

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