[SimpleLoopUnswitch] Fix LCSSA phi node invalidation · llvm/llvm-project@e21dc4b (original) (raw)
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes='print,simple-loop-unswitch,print' -verify-scev < %s 2>/dev/null | FileCheck %s
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; Make sure we don't assert due to insufficient SCEV invalidation.
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define void @test(ptr %p) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[CHECK:%.*]] = icmp eq ptr [[P]], null
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; CHECK-NEXT: br i1 [[CHECK]], label %[[ENTRY_SPLIT_US:.]], label %[[ENTRY_SPLIT:.]]
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; CHECK: [[ENTRY_SPLIT_US]]:
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; CHECK-NEXT: br label %[[BB0_US:.*]]
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; CHECK: [[BB0_US]]:
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; CHECK-NEXT: br label %[[LOOP0_US:.*]]
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; CHECK: [[LOOP0_US]]:
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; CHECK-NEXT: [[V_US:%.*]] = load atomic i32, ptr [[P]] unordered, align 8
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; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[V_US]], 3
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; CHECK-NEXT: br i1 true, label %[[PREHEADER_SPLIT_US:.*]], label %[[BB0_US]]
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; CHECK: [[PREHEADER_SPLIT_US]]:
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; CHECK-NEXT: [[ADD_LCSSA_US:%.*]] = phi i32 [ [[ADD_US]], %[[LOOP0_US]] ]
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; CHECK-NEXT: br label %[[PREHEADER:.*]]
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; CHECK: [[ENTRY_SPLIT]]:
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; CHECK-NEXT: br label %[[BB0:.*]]
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; CHECK: [[BB0]]:
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; CHECK-NEXT: br label %[[LATCH:.*]]
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; CHECK: [[LATCH]]:
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; CHECK-NEXT: br i1 false, label %[[EXIT0:.]], label %[[LOOP0:.]]
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; CHECK: [[EXIT0]]:
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; CHECK-NEXT: ret void
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; CHECK: [[LOOP0]]:
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; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P]] unordered, align 8
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[V]], 3
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; CHECK-NEXT: br i1 true, label %[[PREHEADER_SPLIT:.*]], label %[[BB0]]
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; CHECK: [[PREHEADER_SPLIT]]:
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; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[LOOP0]] ]
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; CHECK-NEXT: br label %[[PREHEADER]]
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; CHECK: [[PREHEADER]]:
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; CHECK-NEXT: [[DOTUS_PHI:%.*]] = phi i32 [ [[ADD_LCSSA]], %[[PREHEADER_SPLIT]] ], [ [[ADD_LCSSA_US]], %[[PREHEADER_SPLIT_US]] ]
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; CHECK-NEXT: br label %[[LOOP1:.*]]
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; CHECK: [[LOOP1]]:
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; CHECK-NEXT: [[IV1:%.]] = phi i32 [ [[DOTUS_PHI]], %[[PREHEADER]] ], [ [[IV1_NEXT:%.]], %[[BACKEDGE:.*]] ]
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; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], -33
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; CHECK-NEXT: br label %[[LOOP2:.*]]
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; CHECK: [[BACKEDGE]]:
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; CHECK-NEXT: br i1 true, label %[[EXIT1:.*]], label %[[LOOP1]]
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; CHECK: [[LOOP2]]:
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; CHECK-NEXT: [[IV0:%.]] = phi i32 [ [[IV1]], %[[LOOP1]] ], [ [[IV0_NEXT:%.]], %[[LOOP2]] ]
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; CHECK-NEXT: [[IV0_NEXT]] = add nsw i32 [[IV0]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[IV0_NEXT]], 0
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; CHECK-NEXT: br i1 [[CMP]], label %[[BACKEDGE]], label %[[LOOP2]]
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; CHECK: [[EXIT1]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%check = icmp eq ptr %p, null
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br label %bb0
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bb0: ; preds = %loop0, %entry
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br i1 %check, label %loop0, label %latch
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latch: ; preds = %bb0
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br i1 %check, label %exit0, label %loop0
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exit0: ; preds = %latch
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ret void
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loop0: ; preds = %latch, %bb0
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%v = load atomic i32, ptr %p unordered, align 8
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%add = add i32 %v, 3
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br i1 true, label %preheader, label %bb0
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preheader: ; preds = %loop0
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br label %loop1
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loop1: ; preds = %backedge, %preheader
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%iv1 = phi i32 [ %add, %preheader ], [ %iv1.next, %backedge ]
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%iv1.next = add i32 %iv1, -33
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br label %loop2
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backedge: ; preds = %loop2
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br i1 true, label %exit1, label %loop1
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loop2: ; preds = %loop2, %loop1
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%iv0 = phi i32 [ %iv1, %loop1 ], [ %iv0.next, %loop2 ]
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%iv0.next = add nsw i32 %iv0, 1
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%cmp = icmp sgt i32 %iv0.next, 0
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br i1 %cmp, label %backedge, label %loop2
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exit1: ; preds = %backedge
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ret void
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}
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