[RISCV] Add target feature to force-enable atomics · llvm/llvm-project@f5ed0cb (original) (raw)
`@@ -105,20 +105,25 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
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`// Pseudo-instructions and codegen patterns
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`//===----------------------------------------------------------------------===//
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``
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let Predicates = [HasStdExtA] in {
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``
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``
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/// Atomic loads and stores
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// Atomic load/store are available under both +a and +force-atomics.
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`// Fences will be inserted for atomic load/stores according to the logic in
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`// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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let Predicates = [HasAtomicLdSt] in {
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defm : LdPat<atomic_load_8, LB>;
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defm : LdPat<atomic_load_16, LH>;
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defm : LdPat<atomic_load_32, LW>;
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+
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defm : AtomicStPat<atomic_store_8, SB, GPR>;
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defm : AtomicStPat<atomic_store_16, SH, GPR>;
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defm : AtomicStPat<atomic_store_32, SW, GPR>;
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}
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``
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defm : LdPat<atomic_load_8, LB>;
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``
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defm : LdPat<atomic_load_16, LH>;
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``
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defm : LdPat<atomic_load_32, LW>;
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let Predicates = [HasAtomicLdSt, IsRV64] in {
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defm : LdPat<atomic_load_64, LD, i64>;
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defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
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}
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defm : AtomicStPat<atomic_store_8, SB, GPR>;
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``
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defm : AtomicStPat<atomic_store_16, SH, GPR>;
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defm : AtomicStPat<atomic_store_32, SW, GPR>;
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let Predicates = [HasStdExtA] in {
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``
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`/// AMOs
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`@@ -304,13 +309,6 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
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`let Predicates = [HasStdExtA, IsRV64] in {
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/// 64-bit atomic loads and stores
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``
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// Fences will be inserted for atomic load/stores according to the logic in
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// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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``
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defm : LdPat<atomic_load_64, LD, i64>;
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``
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defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
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``
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`defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
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`defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;
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`defm : AMOPat<"atomic_load_and_64", "AMOAND_D">;
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