[HEXAGON] Add support to lower "FREEZE a half(f16)" instruction on Hexagon and fix the isel-buildvector-v2f16.ll assertion by quic-asaravan · Pull Request #130977 · llvm/llvm-project (original) (raw)

@llvm/pr-subscribers-backend-hexagon

Author: Abinaya Saravanan (quic-asaravan)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/130977.diff

3 Files Affected:

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index aaa9c65c1e07e..4df88b3a8abd7 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -362,6 +362,7 @@ class HexagonTargetLowering : public TargetLowering { shouldExpandAtomicRMWInIR(AtomicRMWInst AI) const override { return AtomicExpansionKind::LLSC; } + bool softPromoteHalfType() const override { return true; } private: void initializeHVXLowering(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index f77bda3138354..de2bac6905530 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1618,17 +1618,6 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) for (unsigned i = 0; i != Size; ++i) Ops.push_back(Op.getOperand(i)); - // First, split the BUILD_VECTOR for vector pairs. We could generate - // some pairs directly (via splat), but splats should be generated - // by the combiner prior to getting here. - if (VecTy.getSizeInBits() == 16Subtarget.getVectorLength()) { - ArrayRef A(Ops); - MVT SingleTy = typeSplit(VecTy).first; - SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); - SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG); - return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); - }

if (VecTy.getVectorElementType() == MVT::i1) return buildHvxVectorPred(Ops, dl, VecTy, DAG);

@@ -1645,6 +1634,17 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0); }

diff --git a/llvm/test/CodeGen/Hexagon/fp16-promote.ll b/llvm/test/CodeGen/Hexagon/fp16-promote.ll new file mode 100644 index 0000000000000..1ef0a133ce30a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/fp16-promote.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=hexagon < %s | FileCheck %s + +define half @freeze_half_undef() nounwind { +; CHECK-LABEL: freeze_half_undef: +; CHECK: // %bb.0: +; CHECK-NEXT: { +; CHECK-NEXT: call __truncsfhf2 +; CHECK-NEXT: r0 = #0 +; CHECK-NEXT: allocframe(#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: call __extendhfsf2 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: call __truncsfhf2 +; CHECK-NEXT: r0 = sfadd(r0,r0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r31:30 = dealloc_return(r30):raw +; CHECK-NEXT: }