compiler: Fix arm32 asm issues by hierarchically sorting reg classes · rust-lang/rust@0d8f734 (original) (raw)

`@@ -148,22 +148,22 @@ def_regs! {

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` r11: reg = ["r11", "fp"] % frame_pointer_r11,

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` r12: reg = ["r12", "ip"] % not_thumb1,

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` r14: reg = ["r14", "lr"] % not_thumb1,

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s0: sreg, sreg_low16 = ["s0"],

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s1: sreg, sreg_low16 = ["s1"],

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s2: sreg, sreg_low16 = ["s2"],

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s3: sreg, sreg_low16 = ["s3"],

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s4: sreg, sreg_low16 = ["s4"],

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s5: sreg, sreg_low16 = ["s5"],

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s6: sreg, sreg_low16 = ["s6"],

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s7: sreg, sreg_low16 = ["s7"],

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s8: sreg, sreg_low16 = ["s8"],

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s9: sreg, sreg_low16 = ["s9"],

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s10: sreg, sreg_low16 = ["s10"],

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s11: sreg, sreg_low16 = ["s11"],

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s12: sreg, sreg_low16 = ["s12"],

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s13: sreg, sreg_low16 = ["s13"],

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s14: sreg, sreg_low16 = ["s14"],

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s15: sreg, sreg_low16 = ["s15"],

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s0: sreg_low16, sreg = ["s0"],

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s1: sreg_low16, sreg = ["s1"],

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s2: sreg_low16, sreg = ["s2"],

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s3: sreg_low16, sreg = ["s3"],

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s4: sreg_low16, sreg = ["s4"],

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s5: sreg_low16, sreg = ["s5"],

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s6: sreg_low16, sreg = ["s6"],

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s7: sreg_low16, sreg = ["s7"],

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s8: sreg_low16, sreg = ["s8"],

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s9: sreg_low16, sreg = ["s9"],

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s10: sreg_low16, sreg = ["s10"],

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s11: sreg_low16, sreg = ["s11"],

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s12: sreg_low16, sreg = ["s12"],

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s13: sreg_low16, sreg = ["s13"],

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s14: sreg_low16, sreg = ["s14"],

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s15: sreg_low16, sreg = ["s15"],

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` s16: sreg = ["s16"],

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` s17: sreg = ["s17"],

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` s18: sreg = ["s18"],

`@@ -180,22 +180,22 @@ def_regs! {

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` s29: sreg = ["s29"],

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` s30: sreg = ["s30"],

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` s31: sreg = ["s31"],

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d0: dreg, dreg_low16, dreg_low8 = ["d0"],

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d1: dreg, dreg_low16, dreg_low8 = ["d1"],

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d2: dreg, dreg_low16, dreg_low8 = ["d2"],

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d3: dreg, dreg_low16, dreg_low8 = ["d3"],

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d4: dreg, dreg_low16, dreg_low8 = ["d4"],

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d5: dreg, dreg_low16, dreg_low8 = ["d5"],

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d6: dreg, dreg_low16, dreg_low8 = ["d6"],

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d7: dreg, dreg_low16, dreg_low8 = ["d7"],

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d8: dreg, dreg_low16 = ["d8"],

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d9: dreg, dreg_low16 = ["d9"],

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d10: dreg, dreg_low16 = ["d10"],

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d11: dreg, dreg_low16 = ["d11"],

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d12: dreg, dreg_low16 = ["d12"],

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d13: dreg, dreg_low16 = ["d13"],

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d14: dreg, dreg_low16 = ["d14"],

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d15: dreg, dreg_low16 = ["d15"],

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d0: dreg_low8, dreg_low16, dreg = ["d0"],

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d1: dreg_low8, dreg_low16, dreg = ["d1"],

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d2: dreg_low8, dreg_low16, dreg = ["d2"],

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d3: dreg_low8, dreg_low16, dreg = ["d3"],

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d4: dreg_low8, dreg_low16, dreg = ["d4"],

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d5: dreg_low8, dreg_low16, dreg = ["d5"],

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d6: dreg_low8, dreg_low16, dreg = ["d6"],

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d7: dreg_low8, dreg_low16, dreg = ["d7"],

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d8: dreg_low16, dreg = ["d8"],

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d9: dreg_low16, dreg = ["d9"],

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d10: dreg_low16, dreg = ["d10"],

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d11: dreg_low16, dreg = ["d11"],

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d12: dreg_low16, dreg = ["d12"],

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d13: dreg_low16, dreg = ["d13"],

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d14: dreg_low16, dreg = ["d14"],

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d15: dreg_low16, dreg = ["d15"],

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` d16: dreg = ["d16"],

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` d17: dreg = ["d17"],

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` d18: dreg = ["d18"],

`@@ -212,14 +212,14 @@ def_regs! {

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` d29: dreg = ["d29"],

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` d30: dreg = ["d30"],

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` d31: dreg = ["d31"],

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q0: qreg, qreg_low8, qreg_low4 = ["q0"],

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q1: qreg, qreg_low8, qreg_low4 = ["q1"],

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q2: qreg, qreg_low8, qreg_low4 = ["q2"],

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q3: qreg, qreg_low8, qreg_low4 = ["q3"],

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q4: qreg, qreg_low8 = ["q4"],

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q5: qreg, qreg_low8 = ["q5"],

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q6: qreg, qreg_low8 = ["q6"],

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q7: qreg, qreg_low8 = ["q7"],

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q0: qreg_low4, qreg_low8, qreg = ["q0"],

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q1: qreg_low4, qreg_low8, qreg = ["q1"],

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q2: qreg_low4, qreg_low8, qreg = ["q2"],

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q3: qreg_low4, qreg_low8, qreg = ["q3"],

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q4: qreg_low8, qreg = ["q4"],

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q5: qreg_low8, qreg = ["q5"],

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q6: qreg_low8, qreg = ["q6"],

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q7: qreg_low8, qreg = ["q7"],

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` q8: qreg = ["q8"],

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` q9: qreg = ["q9"],

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` q10: qreg = ["q10"],