rustc_target: RISC-V: add base I-related important extensions by a4lg · Pull Request #138823 · rust-lang/rust (original) (raw)

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

This is based on the latest ratified ISA Manuals (version 20240411).

LLVM Definitions:

Additional (1):
One of those, Zicsr, is a dependency of many other ISA extensions and this commit adds correct dependencies to Zicsr.

Additional (2):
In RISC-V, G is an abbreviation of following extensions:

and all RISC-V targets with the G abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates riscv32-wrs-vxworks though).


This is the version 4.
Ztso in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental Ztso requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding Ztso is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry Zihintpause).

Version 4:

Related:

NOT Related but linked:

@rustbot r? @Amanieu
@rustbot label +T-compiler +O-riscv +A-target-feature