RISC-V: Use symbolic instructions on inline assembly (part 2) by a4lg · Pull Request #1936 · rust-lang/stdarch (original) (raw)

While many intrinsics use .insn to generate raw machine code from numbers, all ratified instructions can be now symbolic.

This is the part two (after the pause intrinsic) and uses a different way to use symbolic instructions.

Normally, intrinsics require corresponding extensions and this commit uses newly added Rust target features h and svinval (both representing supervisor-mode extensions), along with the #[target_feature(enable = ...)] attribute.

Note

hinval.vvma and hinval.gvma instructions are a part of the Svinval extension (the H extension is not directly required by LLVM) but denoted to require both h and svinval to show semantic context (they are useful only when the H extension is present and according to the documentation, they are provided only if the hypervisor extension is enabled).

This is the part two after #1927 (currently, this is the superset of it) and requires some Rust compiler changes (adding target features h and svinval; so CI should fail as of this writing).