Jean-daniel Arnould | Institut polytechnique de Grenoble - Grenoble INP (original) (raw)

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Papers by Jean-daniel Arnould

Research paper thumbnail of Un réseau d'adaptation reconfigurable en technologie CMOS SOI pour amplificateur de puissance multimode multi-bandes

HAL (Le Centre pour la Communication Scientifique Directe), Jun 4, 2015

National audienc

Research paper thumbnail of Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip

Research paper thumbnail of A RF tunable impedance matching network with a complete design and measurement methodology

2007 European Microwave Conference, 2007

... Complete Design and Measurement Methodology C. Hoarau1, P.-E. Bailly, J.-D. Arnould, P. Ferra... more ... Complete Design and Measurement Methodology C. Hoarau1, P.-E. Bailly, J.-D. Arnould, P. Ferrari, and P. Xavier ... [7] CE McIntosh, RD Pollard, and RE Miles, “Novel MMIC source-impedance tuners for on-wafer microwave noise-parameter measurements”, IEEE Trans. ...

Research paper thumbnail of Complete Design and Measurement Methodology for a Tunable RF Impedance-Matching Network

IEEE Transactions on Microwave Theory and Techniques, Nov 1, 2008

Research paper thumbnail of A SOI CMOS reconfigurable output matching network for multimode multiband power amplifiers

Research paper thumbnail of General expression for tunable matching network efficiency in the case of complex impedances

Microwave and Optical Technology Letters, Mar 25, 2015

Research paper thumbnail of Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

2022 IEEE International Reliability Physics Symposium (IRPS), Mar 1, 2022

Research paper thumbnail of Modeling and characterization of 0.35 μm CMOS coreless transformer for gate drivers

HAL (Le Centre pour la Communication Scientifique Directe), Apr 1, 2014

In this paper, a monolithic solution based on integrated coreless transformer (ICT) for galvanic ... more In this paper, a monolithic solution based on integrated coreless transformer (ICT) for galvanic isolation and power transfer application is demonstrated. First, the characterization of ICTs is investigated by a set of five devices with stacked topology but different geometrical parameters fabricated in a 0.35 μm H35B4M3 CMOS technology from AMS. Second, the behavior of these ICTs is also predicted by electromagnetic (EM) simulation in Ansoft HFSS and analyzed by their equivalent electrical model. The measured results have shown a peak of voltage gain of -3 dB with the design of 300 μm of diameter while charging with the input capacitance of 900 fF of the demodulated circuit. Finally, an integrated gate driver is also fabricated using the optimal design of ICT, achieving a compact area of 0.72 mm2 and offers 1.8 kV of isolation. The experimental results of this gate driver have validated the use of isolated signal and energy transfer by on-chip transformer for both high side and low side applications.

Research paper thumbnail of Méthode de conception d’amplificateurs distribués millimétriques basée sur la matrice chaîne (ABCD) 4 ports

HAL (Le Centre pour la Communication Scientifique Directe), Jun 7, 2022

Research paper thumbnail of Analysis of input receiver transistors behavior during a CDM event

2022 44th Annual EOS/ESD Symposium (EOS/ESD)

Research paper thumbnail of Accurate Design Method for Millimeter Wave Distributed Amplifier Based on Four-Port Chain (ABCD) Matrix Model

IEEE Transactions on Circuits and Systems I: Regular Papers

Research paper thumbnail of Mesures et modélisation RF de capacités MIM intégrées

J3eA

Il s’agit de former des étudiants de Master 2 et des ingénieurs en formation continue à la mesure... more Il s’agit de former des étudiants de Master 2 et des ingénieurs en formation continue à la mesure RF sous pointes pour caractériser des capacités Métal-Isolant-Métal (MIM) intégrées sur un wafer. La problématique est d’obtenir le modèle électrique le plus fiable possible de ces capacités entre 40MHz et 26GHz tout en s’affranchissant des contraintes de mesures et des éléments d’accès RF à cette capacité.

Research paper thumbnail of Système de mesure intégré millimétrique en bande G :140-220GHz

Research paper thumbnail of Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies

IEEE Solid-State Circuits Letters

Research paper thumbnail of A G band +2 dBm balanced frequency doubler in 55 nm SiGe BiCMOS

2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2017

In this paper, a new balanced frequency doubler based on a Marchand Balun with Coupled Slow-wave ... more In this paper, a new balanced frequency doubler based on a Marchand Balun with Coupled Slow-wave Coplanar Wave (CS-CPW) lines in G band is presented and analyzed. The experimental results of the frequency doubler exhibit at 174 GHz a peak output power of +2 dBm associate with a linear conversion gain of −3.8 dB, a frequency bandwidth of 160 to 190 GHz and a DC power consumption of 25 mW. This doubler is fabricated in a 55 nm SiGe BiCMOS technology from STMicroelectronics with ft/fmax 320/370 GHz respectively and an area of 1200×700 µm2 including the pads.

Research paper thumbnail of Integrated gate driver circuits with an ultra-compact design and high level of galvanic isolation for power transistors

Research paper thumbnail of Caractérisation de capacités MIM Cu-Si3N4-Cu en technologie CMOS 0,12 µm pour des applications radiofréquences

Research paper thumbnail of Caractérisation électrique de l'isolant inter-armature de capacités Cu-Si3N4-Cu entre 45 MHz et 40 GHz en technologie CMOS 120nm

Research paper thumbnail of Filtre ULB basé sur des structures périodiques sinusoïdales

Research paper thumbnail of Potentialités des structures magnétiques pour les fonctions RF reconfigurables

Research paper thumbnail of Un réseau d'adaptation reconfigurable en technologie CMOS SOI pour amplificateur de puissance multimode multi-bandes

HAL (Le Centre pour la Communication Scientifique Directe), Jun 4, 2015

National audienc

Research paper thumbnail of Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip

Research paper thumbnail of A RF tunable impedance matching network with a complete design and measurement methodology

2007 European Microwave Conference, 2007

... Complete Design and Measurement Methodology C. Hoarau1, P.-E. Bailly, J.-D. Arnould, P. Ferra... more ... Complete Design and Measurement Methodology C. Hoarau1, P.-E. Bailly, J.-D. Arnould, P. Ferrari, and P. Xavier ... [7] CE McIntosh, RD Pollard, and RE Miles, “Novel MMIC source-impedance tuners for on-wafer microwave noise-parameter measurements”, IEEE Trans. ...

Research paper thumbnail of Complete Design and Measurement Methodology for a Tunable RF Impedance-Matching Network

IEEE Transactions on Microwave Theory and Techniques, Nov 1, 2008

Research paper thumbnail of A SOI CMOS reconfigurable output matching network for multimode multiband power amplifiers

Research paper thumbnail of General expression for tunable matching network efficiency in the case of complex impedances

Microwave and Optical Technology Letters, Mar 25, 2015

Research paper thumbnail of Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

2022 IEEE International Reliability Physics Symposium (IRPS), Mar 1, 2022

Research paper thumbnail of Modeling and characterization of 0.35 μm CMOS coreless transformer for gate drivers

HAL (Le Centre pour la Communication Scientifique Directe), Apr 1, 2014

In this paper, a monolithic solution based on integrated coreless transformer (ICT) for galvanic ... more In this paper, a monolithic solution based on integrated coreless transformer (ICT) for galvanic isolation and power transfer application is demonstrated. First, the characterization of ICTs is investigated by a set of five devices with stacked topology but different geometrical parameters fabricated in a 0.35 μm H35B4M3 CMOS technology from AMS. Second, the behavior of these ICTs is also predicted by electromagnetic (EM) simulation in Ansoft HFSS and analyzed by their equivalent electrical model. The measured results have shown a peak of voltage gain of -3 dB with the design of 300 μm of diameter while charging with the input capacitance of 900 fF of the demodulated circuit. Finally, an integrated gate driver is also fabricated using the optimal design of ICT, achieving a compact area of 0.72 mm2 and offers 1.8 kV of isolation. The experimental results of this gate driver have validated the use of isolated signal and energy transfer by on-chip transformer for both high side and low side applications.

Research paper thumbnail of Méthode de conception d’amplificateurs distribués millimétriques basée sur la matrice chaîne (ABCD) 4 ports

HAL (Le Centre pour la Communication Scientifique Directe), Jun 7, 2022

Research paper thumbnail of Analysis of input receiver transistors behavior during a CDM event

2022 44th Annual EOS/ESD Symposium (EOS/ESD)

Research paper thumbnail of Accurate Design Method for Millimeter Wave Distributed Amplifier Based on Four-Port Chain (ABCD) Matrix Model

IEEE Transactions on Circuits and Systems I: Regular Papers

Research paper thumbnail of Mesures et modélisation RF de capacités MIM intégrées

J3eA

Il s’agit de former des étudiants de Master 2 et des ingénieurs en formation continue à la mesure... more Il s’agit de former des étudiants de Master 2 et des ingénieurs en formation continue à la mesure RF sous pointes pour caractériser des capacités Métal-Isolant-Métal (MIM) intégrées sur un wafer. La problématique est d’obtenir le modèle électrique le plus fiable possible de ces capacités entre 40MHz et 26GHz tout en s’affranchissant des contraintes de mesures et des éléments d’accès RF à cette capacité.

Research paper thumbnail of Système de mesure intégré millimétrique en bande G :140-220GHz

Research paper thumbnail of Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies

IEEE Solid-State Circuits Letters

Research paper thumbnail of A G band +2 dBm balanced frequency doubler in 55 nm SiGe BiCMOS

2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2017

In this paper, a new balanced frequency doubler based on a Marchand Balun with Coupled Slow-wave ... more In this paper, a new balanced frequency doubler based on a Marchand Balun with Coupled Slow-wave Coplanar Wave (CS-CPW) lines in G band is presented and analyzed. The experimental results of the frequency doubler exhibit at 174 GHz a peak output power of +2 dBm associate with a linear conversion gain of −3.8 dB, a frequency bandwidth of 160 to 190 GHz and a DC power consumption of 25 mW. This doubler is fabricated in a 55 nm SiGe BiCMOS technology from STMicroelectronics with ft/fmax 320/370 GHz respectively and an area of 1200×700 µm2 including the pads.

Research paper thumbnail of Integrated gate driver circuits with an ultra-compact design and high level of galvanic isolation for power transistors

Research paper thumbnail of Caractérisation de capacités MIM Cu-Si3N4-Cu en technologie CMOS 0,12 µm pour des applications radiofréquences

Research paper thumbnail of Caractérisation électrique de l'isolant inter-armature de capacités Cu-Si3N4-Cu entre 45 MHz et 40 GHz en technologie CMOS 120nm

Research paper thumbnail of Filtre ULB basé sur des structures périodiques sinusoïdales

Research paper thumbnail of Potentialités des structures magnétiques pour les fonctions RF reconfigurables

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