Amr Abdel-Hamid - Profile on Academia.edu (original) (raw)

Papers by Amr Abdel-Hamid

Intellectual property (IP) blocks reuse is essential for facilitating the design process of syste... more Intellectual property (IP) blocks reuse is essential for facilitating the design process of system-on-a-chip. Sharing IP designs still poses significant high security risks not only to copyright but also to design authenticity. Intruders, or even competitors, can make design changes to IPs, which can lead to the loss of the owner's credibility. In this paper, we are trying to solve such challenge by proposing a novel fragile IP watermarking technique. The proposed technique protects hardware designs from alteration or any modifications that might occur to the design. The approach utilizes existing transitions in a finite state machine (FSM) component of an IP and does not result on any overhead to the IP design. Finally, we implemented the algorithm proposed and tested it.

Computer and Information Science, Jan 27, 2018

The IEEE 802.15.4 standard defines the PHY and MAC layer specifications for Low-Rate Wireless Per... more The IEEE 802.15.4 standard defines the PHY and MAC layer specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs). With the proliferation of many time-critical applications with real-time delivery, low latency, and/or specific bandwidth requirements, Guaranteed Time Slots (GTS) are increasingly being used for reliable contention-free data transmission by nodes within beacon-enabled WPANs. To evaluate the performance of the 802.15.4 GTS management scheme, this paper introduces a new GTS simulation model for OMNeT++ / MiXiM. Our GTS model considers star-topology WPANs within the 2.4 GHz frequency band, and is in full conformance with the IEEE 802.15.4-2006 standard. To enable thorough investigation of the behaviors and impacts of different attacks against the 802.15.4 GTS mechanism, a new GTS attacks simulation model for OMNeT++ is also introduced in this paper. Our GTS attacks model is developed for OMNeT++ / NETA, and is integrated with our GTS model to provide a single inclusive OMNeT++ simulation model for both the GTS mechanism and all known-to-date attacks against it.

Journal of Electrical and Computer Engineering, 2016

The IEEE 802.15.4 standard has been established as the dominant enabling technology for Wireless ... more The IEEE 802.15.4 standard has been established as the dominant enabling technology for Wireless Sensor Networks (WSNs). With the proliferation of security-sensitive applications involving WSNs, WSN security has become a topic of great significance. In comparison with traditional wired and wireless networks, WSNs possess additional vulnerabilities which present opportunities for attackers to launch novel and more complicated attacks against such networks. For this reason, a thorough investigation of attacks against WSNs is required. This paper provides a single unified survey that dissects all IEEE 802.15.4 PHY and MAC layer attacks known to date. While the majority of existing references investigate the motive and behavior of each attack separately, this survey classifies the attacks according to clear metrics within the paper and addresses the interrelationships and differences between the attacks following their classification. The authors' opinions and comments regarding the placement of the attacks within the defined classifications are also provided. A comparative analysis between the classified attacks is then performed with respect to a set of defined evaluation criteria. The first half of this paper addresses attacks on the IEEE 802.15.4 PHY layer, whereas the second half of the paper addresses IEEE 802.15.4 MAC layer attacks.

On Detecting IoT Power Signature Anomalies using Hidden Markov Model (HMM)

The internet of thing (IoT) has become a widespread phenomenon that has resulted in an exponentia... more The internet of thing (IoT) has become a widespread phenomenon that has resulted in an exponential growth in data. The increase in the number of devices connected to the internet has raised a lot of security issues and privacy concerns. Users are susceptible to many forms of cyber-attacks; which could affect the functionality of their devices and their power signature. In this paper, we are proposing the usage of Hidden Markov Model (HMM) to model the power consumption patterns of IoT sensor nodes. Using such model, we were able to detect anomalies in the system's behavior and thus, identifying attacks and classifying them. Using the training data, a detection threshold is computed to differentiate between normal and anomalous behavior. A series of tests were performed on the algorithm using false data injection and the effect of varying HMM parameters is studied. Finally, alterations to the IoT sensor node's functionality are made to mimic the effect of an attack. The method was found to be successful in identifying attacks, trojans and malfunctions as well as, detecting the type of change that has occurred in the system's performance.

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., Dec 23, 2004

Abslracl-Intellectual property (IP) block reuse is essential for facilitating the design process ... more Abslracl-Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip (SOC). Sharing IY blocks in such a competitive market poses signiticant high security risks. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of 1P blocks. In this paper, we present an automatic tool for watermarking sequential IP designs. The tool is based on the idea of utilizing unused transitions in the State Transition Graph (STG) to add a part of the watermark. The tool also tries to create a supraliminal channel hy utilizing the already existing transitions. The paper describes the structure of the tool, overviews the algorithms used in it. components, and reports experimental results obtained by applying it on a set of benchmarks.

Classification and analysis of IEEE 802.15.4 MAC layer attacks

IEEE 802.15.4 Wireless Sensor Networks (WSNs) possess additional vulnerabilities in comparison wi... more IEEE 802.15.4 Wireless Sensor Networks (WSNs) possess additional vulnerabilities in comparison with traditional wired and wireless networks, such as broadcast nature of wireless medium, dynamic network topology, resource- constrained nodes, lack of physical safeguards in nodes, and immense network scale. These inherent vulnerabilities present opportunities for attackers to launch novel and more complicated attacks against such networks. For this reason, a thorough investigation of the attacks which can be launched against WSNs is required. This paper provides a single unified survey that dissects all IEEE 802.15.4 MAC layer attacks known to date. While the majority of existing references investigate the motive and behavior of each attack separately, this survey addresses the interrelationships and differences between the attacks following their classification. The survey defines two main classifications for the attacks by combining and refining existing classifications of the attacks obtained from external references. The defined classifications are further extended by including additional attacks, which have been left out by other references, within the classifications. The authors' opinions and comments regarding the placement of the attacks within the defined classifications are also provided. A comparative analysis between the classified attacks is then performed with respect to a set of evaluation criteria defined within the paper.

Affirming Hardware Design Authenticity Using Fragile IP Watermarking

The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry t... more The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry to move its fabrication facilities to cheaper less reliable sources. This process creates the chance of inserting malicious manipulations namely Hardware Trojans at different phases of the design cycle. Trojans are a real challenge to IC industry especially in an era of smart cities and connected sensors. In this paper, we propose a behavioral fragile IP watermarking technique that embeds the signature in finite state machines (FSMs) transitions to ensure design integrity. The inserted fragile mark is extremely sensitive to any design alterations, which makes it an excellent and economical choice to detect design changes. Finally, we analyze and evaluate different aspects of the proposed technique, including sensitivity to design changes, robustness, as well as complexity and insertion overhead to design cycle.

Design, Automation, and Test in Europe, Apr 1, 2005

Sharing IP blocks in today's competitive market poses significant high security risks. Creators a... more Sharing IP blocks in today's competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illegally redistributed by consumers, and consumers want assurances that the content they buy is legitimate. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we propose a new approach for watermarking IP designs based on the embedding of the ownership proof as part of the IP design's FSM. The approach utilizes coinciding as well as, unused transitions in the state transition graph of the design. Our approach increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. We also defin evaluation criteria for our approach, and us experimental measures to prove its robustness.

Fragile HFSM Watermarking Hardware IP Authentication CAD Tool

Hardware Trojans are intrusive actions that tend to corrupt the functional behavior of genuine de... more Hardware Trojans are intrusive actions that tend to corrupt the functional behavior of genuine designs, leak their sensitive information, or even downgrade their performance. This paper proposes a Computer-Aided Design (CAD) tool for Fragile Hierarchical FSM Watermarking to be employed as a novel presilicon Trojan detection technique at the RTL level. The performance of the proposed watermarking tool, regarding its complexity and insertion time overhead, is evaluated. Moreover, an intentional Trojan insertion scenario is executed in order to verify the sensitivity and reliability of the presented tool against the least changes in the original RTL design.

Sharing Intellectual Property (IP) blocks in today's competitive market poses significant high se... more Sharing Intellectual Property (IP) blocks in today's competitive market poses significant high security risks. In this paper, we present a tutorial for a watermarking approach based on the embedding of the ownership proof as part of the IP design's finite state machine (FSM). It utilizes coinciding as well as unused transitions in the state transition graph of the design. Based on this approach, we have developed a robust watermarking framework, used for copyright protection. The developed technique increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. In order to integrate these algorithms in the design cycle of industrial projects, we extend the above techniques to enable the watermarking of hierarchical finite state machines (HFSMs).

Intellectual property (IP) block reuse is essential for facilitating the design process of System... more Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant high security risks. IPs can be read, copied or even partitioned to cover the authorship proof. Creators and owners of IP designs want assurance that their content will not be illegally redistributed by consumers. Consumers, on the other hand, want assurance that the content they buy is legitimate. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of IP blocks. In this paper, we outline IP watermarking and survey the current stateof-the-art of different schemes and algorithms. We also highlight the main technical problems that should be solved in order to let IP watermarking be used widely in industry.

In this work, we have formalized and verified a hardware implementation of the Table-Driven algor... more In this work, we have formalized and verified a hardware implementation of the Table-Driven algorithm for the floating-point exponential function. We have used a hierarchical approach enabling the verification of this function from the gate level implementation up to a behavioral specification adapted from the high level algorithmic description written by Harrison [3].

IEEE Access

Diabetic Retinopathy (DR)-a complication developed due to heightened blood glucose levelsis deeme... more Diabetic Retinopathy (DR)-a complication developed due to heightened blood glucose levelsis deemed one of the most sight-threatening diseases. Unfortunately, DR screening is manually acquired by an ophthalmologist, a process that can be considered erroneous and time-consuming. Accordingly, automated DR diagnostics have become a focus of research in recent years due to the tremendous increase in diabetic patients. Moreover, the recent accomplishments demonstrated by Convolutional Neural Networks (CNN) settle them as state-of-the-art for DR stage identification. This paper proposes a new automatic deeplearning-based approach for severity detection by utilizing a single Color Fundus photograph (CFP). The proposed technique employs DenseNet169's encoder to construct a visual embedding. Furthermore, Convolutional Block Attention Module (CBAM) is introduced on top of the encoder to reinforce its discriminative power. Finally, the model is trained using cross-entropy loss on the Kaggle Asia Pacific Tele-Ophthalmology Society's (APTOS) dataset. On the binary classification task, we accomplished (97% accuracy-97% sensitivity-98.3% specificity-0.9455, Quadratic Weighted Kappa score (QWK)) compared to the state-of-the-art. Moreover, Our network showed high competency (82% accuracy-0.888 (QWK)) for severity grading. The significant contribution of the proposed framework is that it efficiently grades the severity level of diabetic retinopathy while reducing the time and space complexity required, which demonstrates it as a promising candidate for autonomous diagnosis. INDEX TERMS Diabetic retinopathy, convolutional neural networks (CNN), attention mechanism, deep learning.

2011 AGILE Conference, 2011

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011

Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new ... more Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new FSM watermarking scheme is proposed by making the authorship information a non-redundant property of the FSM. To overcome the vulnerability to state removal attack and minimize the design overhead, the watermark bits are seamlessly interwoven into the outputs of the existing and free transitions of state transition graph (STG). Unlike other transition-based STG watermarking, pseudo input variables have been reduced and made functionally indiscernible by the notion of reserved free literal. The assignment of reserved literals is exploited to minimize the overhead of watermarking and make the watermarked FSM fallible upon removal of any pseudo input variable. A direct and convenient detection scheme is also proposed to allow the watermark on the FSM to be publicly detectable. Experimental results on the watermarked circuits from the ISCAS'89 and IWLS'93 benchmark sets show lower or acceptably low overheads with higher tamper resilience and stronger authorship proof in comparison with related watermarking schemes for sequential functions.

Affirming Hardware Design Authenticity Using Fragile IP Watermarking

2018 International Conference on Computer and Applications (ICCA)

The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry t... more The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry to move its fabrication facilities to cheaper less reliable sources. This process creates the chance of inserting malicious manipulations namely Hardware Trojans at different phases of the design cycle. Trojans are a real challenge to IC industry especially in an era of smart cities and connected sensors. In this paper, we propose a behavioral fragile IP watermarking technique that embeds the signature in finite state machines (FSMs) transitions to ensure design integrity. The inserted fragile mark is extremely sensitive to any design alterations, which makes it an excellent and economical choice to detect design changes. Finally, we analyze and evaluate different aspects of the proposed technique, including sensitivity to design changes, robustness, as well as complexity and insertion overhead to design cycle.

Abstract. The IEEE-754 floating-point standard is considered one of the most important standards,... more Abstract. The IEEE-754 floating-point standard is considered one of the most important standards, and is used in nearly all floating-point applications. In this paper, we have formalized and verified a hardware implementation of the Table-Driven algorithm for the floating-point exponential function. Throughout this paper, we have used a hierarchical approach in formally modeling and verifying in HOL the floating-point exponential function from the gate level implementation up to a behavioral specification written by Harrison [7]. 1

Deep datapath and algorithm complexity have made the verification of floating-point units a very ... more Deep datapath and algorithm complexity have made the verification of floating-point units a very hard task. Most simulation and reachability analysis verification tools fail to verify a circuit with a deep datapath like most industrial floating-point units. Theorem proving, however, offers a better solution to handle such verification. In this paper, we have hierarchically formalized and verified a hardware implementation of the IEEE-754 table-driven floating-point exponential function algorithm using the higher-order logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from gate-level implementation of the circuit up to a high-level mathematical specification.

Intellectual property (IP) blocks reuse is essential for facilitating the design process of syste... more Intellectual property (IP) blocks reuse is essential for facilitating the design process of system-on-a-chip. Sharing IP designs still poses significant high security risks not only to copyright but also to design authenticity. Intruders, or even competitors, can make design changes to IPs, which can lead to the loss of the owner's credibility. In this paper, we are trying to solve such challenge by proposing a novel fragile IP watermarking technique. The proposed technique protects hardware designs from alteration or any modifications that might occur to the design. The approach utilizes existing transitions in a finite state machine (FSM) component of an IP and does not result on any overhead to the IP design. Finally, we implemented the algorithm proposed and tested it.

Computer and Information Science, Jan 27, 2018

The IEEE 802.15.4 standard defines the PHY and MAC layer specifications for Low-Rate Wireless Per... more The IEEE 802.15.4 standard defines the PHY and MAC layer specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs). With the proliferation of many time-critical applications with real-time delivery, low latency, and/or specific bandwidth requirements, Guaranteed Time Slots (GTS) are increasingly being used for reliable contention-free data transmission by nodes within beacon-enabled WPANs. To evaluate the performance of the 802.15.4 GTS management scheme, this paper introduces a new GTS simulation model for OMNeT++ / MiXiM. Our GTS model considers star-topology WPANs within the 2.4 GHz frequency band, and is in full conformance with the IEEE 802.15.4-2006 standard. To enable thorough investigation of the behaviors and impacts of different attacks against the 802.15.4 GTS mechanism, a new GTS attacks simulation model for OMNeT++ is also introduced in this paper. Our GTS attacks model is developed for OMNeT++ / NETA, and is integrated with our GTS model to provide a single inclusive OMNeT++ simulation model for both the GTS mechanism and all known-to-date attacks against it.

Journal of Electrical and Computer Engineering, 2016

The IEEE 802.15.4 standard has been established as the dominant enabling technology for Wireless ... more The IEEE 802.15.4 standard has been established as the dominant enabling technology for Wireless Sensor Networks (WSNs). With the proliferation of security-sensitive applications involving WSNs, WSN security has become a topic of great significance. In comparison with traditional wired and wireless networks, WSNs possess additional vulnerabilities which present opportunities for attackers to launch novel and more complicated attacks against such networks. For this reason, a thorough investigation of attacks against WSNs is required. This paper provides a single unified survey that dissects all IEEE 802.15.4 PHY and MAC layer attacks known to date. While the majority of existing references investigate the motive and behavior of each attack separately, this survey classifies the attacks according to clear metrics within the paper and addresses the interrelationships and differences between the attacks following their classification. The authors' opinions and comments regarding the placement of the attacks within the defined classifications are also provided. A comparative analysis between the classified attacks is then performed with respect to a set of defined evaluation criteria. The first half of this paper addresses attacks on the IEEE 802.15.4 PHY layer, whereas the second half of the paper addresses IEEE 802.15.4 MAC layer attacks.

On Detecting IoT Power Signature Anomalies using Hidden Markov Model (HMM)

The internet of thing (IoT) has become a widespread phenomenon that has resulted in an exponentia... more The internet of thing (IoT) has become a widespread phenomenon that has resulted in an exponential growth in data. The increase in the number of devices connected to the internet has raised a lot of security issues and privacy concerns. Users are susceptible to many forms of cyber-attacks; which could affect the functionality of their devices and their power signature. In this paper, we are proposing the usage of Hidden Markov Model (HMM) to model the power consumption patterns of IoT sensor nodes. Using such model, we were able to detect anomalies in the system's behavior and thus, identifying attacks and classifying them. Using the training data, a detection threshold is computed to differentiate between normal and anomalous behavior. A series of tests were performed on the algorithm using false data injection and the effect of varying HMM parameters is studied. Finally, alterations to the IoT sensor node's functionality are made to mimic the effect of an attack. The method was found to be successful in identifying attacks, trojans and malfunctions as well as, detecting the type of change that has occurred in the system's performance.

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., Dec 23, 2004

Abslracl-Intellectual property (IP) block reuse is essential for facilitating the design process ... more Abslracl-Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip (SOC). Sharing IY blocks in such a competitive market poses signiticant high security risks. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of 1P blocks. In this paper, we present an automatic tool for watermarking sequential IP designs. The tool is based on the idea of utilizing unused transitions in the State Transition Graph (STG) to add a part of the watermark. The tool also tries to create a supraliminal channel hy utilizing the already existing transitions. The paper describes the structure of the tool, overviews the algorithms used in it. components, and reports experimental results obtained by applying it on a set of benchmarks.

Classification and analysis of IEEE 802.15.4 MAC layer attacks

IEEE 802.15.4 Wireless Sensor Networks (WSNs) possess additional vulnerabilities in comparison wi... more IEEE 802.15.4 Wireless Sensor Networks (WSNs) possess additional vulnerabilities in comparison with traditional wired and wireless networks, such as broadcast nature of wireless medium, dynamic network topology, resource- constrained nodes, lack of physical safeguards in nodes, and immense network scale. These inherent vulnerabilities present opportunities for attackers to launch novel and more complicated attacks against such networks. For this reason, a thorough investigation of the attacks which can be launched against WSNs is required. This paper provides a single unified survey that dissects all IEEE 802.15.4 MAC layer attacks known to date. While the majority of existing references investigate the motive and behavior of each attack separately, this survey addresses the interrelationships and differences between the attacks following their classification. The survey defines two main classifications for the attacks by combining and refining existing classifications of the attacks obtained from external references. The defined classifications are further extended by including additional attacks, which have been left out by other references, within the classifications. The authors' opinions and comments regarding the placement of the attacks within the defined classifications are also provided. A comparative analysis between the classified attacks is then performed with respect to a set of evaluation criteria defined within the paper.

Affirming Hardware Design Authenticity Using Fragile IP Watermarking

The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry t... more The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry to move its fabrication facilities to cheaper less reliable sources. This process creates the chance of inserting malicious manipulations namely Hardware Trojans at different phases of the design cycle. Trojans are a real challenge to IC industry especially in an era of smart cities and connected sensors. In this paper, we propose a behavioral fragile IP watermarking technique that embeds the signature in finite state machines (FSMs) transitions to ensure design integrity. The inserted fragile mark is extremely sensitive to any design alterations, which makes it an excellent and economical choice to detect design changes. Finally, we analyze and evaluate different aspects of the proposed technique, including sensitivity to design changes, robustness, as well as complexity and insertion overhead to design cycle.

Design, Automation, and Test in Europe, Apr 1, 2005

Sharing IP blocks in today's competitive market poses significant high security risks. Creators a... more Sharing IP blocks in today's competitive market poses significant high security risks. Creators and owners of IP designs want assurances that their content will not be illegally redistributed by consumers, and consumers want assurances that the content they buy is legitimate. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we propose a new approach for watermarking IP designs based on the embedding of the ownership proof as part of the IP design's FSM. The approach utilizes coinciding as well as, unused transitions in the state transition graph of the design. Our approach increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. We also defin evaluation criteria for our approach, and us experimental measures to prove its robustness.

Fragile HFSM Watermarking Hardware IP Authentication CAD Tool

Hardware Trojans are intrusive actions that tend to corrupt the functional behavior of genuine de... more Hardware Trojans are intrusive actions that tend to corrupt the functional behavior of genuine designs, leak their sensitive information, or even downgrade their performance. This paper proposes a Computer-Aided Design (CAD) tool for Fragile Hierarchical FSM Watermarking to be employed as a novel presilicon Trojan detection technique at the RTL level. The performance of the proposed watermarking tool, regarding its complexity and insertion time overhead, is evaluated. Moreover, an intentional Trojan insertion scenario is executed in order to verify the sensitivity and reliability of the presented tool against the least changes in the original RTL design.

Sharing Intellectual Property (IP) blocks in today's competitive market poses significant high se... more Sharing Intellectual Property (IP) blocks in today's competitive market poses significant high security risks. In this paper, we present a tutorial for a watermarking approach based on the embedding of the ownership proof as part of the IP design's finite state machine (FSM). It utilizes coinciding as well as unused transitions in the state transition graph of the design. Based on this approach, we have developed a robust watermarking framework, used for copyright protection. The developed technique increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. In order to integrate these algorithms in the design cycle of industrial projects, we extend the above techniques to enable the watermarking of hierarchical finite state machines (HFSMs).

Intellectual property (IP) block reuse is essential for facilitating the design process of System... more Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant high security risks. IPs can be read, copied or even partitioned to cover the authorship proof. Creators and owners of IP designs want assurance that their content will not be illegally redistributed by consumers. Consumers, on the other hand, want assurance that the content they buy is legitimate. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of IP blocks. In this paper, we outline IP watermarking and survey the current stateof-the-art of different schemes and algorithms. We also highlight the main technical problems that should be solved in order to let IP watermarking be used widely in industry.

In this work, we have formalized and verified a hardware implementation of the Table-Driven algor... more In this work, we have formalized and verified a hardware implementation of the Table-Driven algorithm for the floating-point exponential function. We have used a hierarchical approach enabling the verification of this function from the gate level implementation up to a behavioral specification adapted from the high level algorithmic description written by Harrison [3].

IEEE Access

Diabetic Retinopathy (DR)-a complication developed due to heightened blood glucose levelsis deeme... more Diabetic Retinopathy (DR)-a complication developed due to heightened blood glucose levelsis deemed one of the most sight-threatening diseases. Unfortunately, DR screening is manually acquired by an ophthalmologist, a process that can be considered erroneous and time-consuming. Accordingly, automated DR diagnostics have become a focus of research in recent years due to the tremendous increase in diabetic patients. Moreover, the recent accomplishments demonstrated by Convolutional Neural Networks (CNN) settle them as state-of-the-art for DR stage identification. This paper proposes a new automatic deeplearning-based approach for severity detection by utilizing a single Color Fundus photograph (CFP). The proposed technique employs DenseNet169's encoder to construct a visual embedding. Furthermore, Convolutional Block Attention Module (CBAM) is introduced on top of the encoder to reinforce its discriminative power. Finally, the model is trained using cross-entropy loss on the Kaggle Asia Pacific Tele-Ophthalmology Society's (APTOS) dataset. On the binary classification task, we accomplished (97% accuracy-97% sensitivity-98.3% specificity-0.9455, Quadratic Weighted Kappa score (QWK)) compared to the state-of-the-art. Moreover, Our network showed high competency (82% accuracy-0.888 (QWK)) for severity grading. The significant contribution of the proposed framework is that it efficiently grades the severity level of diabetic retinopathy while reducing the time and space complexity required, which demonstrates it as a promising candidate for autonomous diagnosis. INDEX TERMS Diabetic retinopathy, convolutional neural networks (CNN), attention mechanism, deep learning.

2011 AGILE Conference, 2011

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011

Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new ... more Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a new FSM watermarking scheme is proposed by making the authorship information a non-redundant property of the FSM. To overcome the vulnerability to state removal attack and minimize the design overhead, the watermark bits are seamlessly interwoven into the outputs of the existing and free transitions of state transition graph (STG). Unlike other transition-based STG watermarking, pseudo input variables have been reduced and made functionally indiscernible by the notion of reserved free literal. The assignment of reserved literals is exploited to minimize the overhead of watermarking and make the watermarked FSM fallible upon removal of any pseudo input variable. A direct and convenient detection scheme is also proposed to allow the watermark on the FSM to be publicly detectable. Experimental results on the watermarked circuits from the ISCAS'89 and IWLS'93 benchmark sets show lower or acceptably low overheads with higher tamper resilience and stronger authorship proof in comparison with related watermarking schemes for sequential functions.

Affirming Hardware Design Authenticity Using Fragile IP Watermarking

2018 International Conference on Computer and Applications (ICCA)

The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry t... more The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry to move its fabrication facilities to cheaper less reliable sources. This process creates the chance of inserting malicious manipulations namely Hardware Trojans at different phases of the design cycle. Trojans are a real challenge to IC industry especially in an era of smart cities and connected sensors. In this paper, we propose a behavioral fragile IP watermarking technique that embeds the signature in finite state machines (FSMs) transitions to ensure design integrity. The inserted fragile mark is extremely sensitive to any design alterations, which makes it an excellent and economical choice to detect design changes. Finally, we analyze and evaluate different aspects of the proposed technique, including sensitivity to design changes, robustness, as well as complexity and insertion overhead to design cycle.

Abstract. The IEEE-754 floating-point standard is considered one of the most important standards,... more Abstract. The IEEE-754 floating-point standard is considered one of the most important standards, and is used in nearly all floating-point applications. In this paper, we have formalized and verified a hardware implementation of the Table-Driven algorithm for the floating-point exponential function. Throughout this paper, we have used a hierarchical approach in formally modeling and verifying in HOL the floating-point exponential function from the gate level implementation up to a behavioral specification written by Harrison [7]. 1

Deep datapath and algorithm complexity have made the verification of floating-point units a very ... more Deep datapath and algorithm complexity have made the verification of floating-point units a very hard task. Most simulation and reachability analysis verification tools fail to verify a circuit with a deep datapath like most industrial floating-point units. Theorem proving, however, offers a better solution to handle such verification. In this paper, we have hierarchically formalized and verified a hardware implementation of the IEEE-754 table-driven floating-point exponential function algorithm using the higher-order logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from gate-level implementation of the circuit up to a high-level mathematical specification.