More accurate complex multiplication for embedded processors (original) (raw)

Communication Dans Un Congrès Année : 2017

Résumé

This paper presents some work in progress on the development of fast and accurate support for complex floating-point arithmetic on embedded processors. Focusing on the case of multiplication, we describe algorithms and implementations for computing both the real and imaginary parts with high relative accuracy. We show that, in practice, such accuracy guarantees can be achieved with reasonable overhead compared with conventional algorithms (which are those offered by current implementations and for which the real or imaginary part of a product can have no correct digit at all). For example, the average execution-time overheads when computing an FFT on the ARM Cortex-A53 and -A57 processors range from 1.04x to 1.17x only, while arithmetic costs suggest overheads from 1.5x to 1.8x.

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https://hal.science/hal-01512760

Soumis le : jeudi 11 mai 2017-15:17:22

Dernière modification le : vendredi 24 octobre 2025-17:40:02

Archivage à long terme le : samedi 12 août 2017-13:37:21

Dates et versions

hal-01512760 , version 1 (24-04-2017)

hal-01512760 , version 2 (11-05-2017)

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Claude-Pierre Jeannerod, Christophe Monat, Laurent Thévenoux. More accurate complex multiplication for embedded processors. 12th IEEE International Symposium on Industrial Embedded Systems (SIES 2017), Jun 2017, Toulouse, France. ⟨hal-01512760v2⟩

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