Daniel Studzinski | Hochschule für Technik und Wirtschaft, HTW Berlin (original) (raw)
Address: Singapore, Singapore
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The present invention relates to a method for producing a firmly adhering metal-coated functional... more The present invention relates to a method for producing a firmly adhering metal-coated functional element comprising a base body and a coated thereon a metal coating, said metal coating is applied directly on the base body, but to a one acrylonitrile-containing gas before on the base body by means of a plasma polymerisation or vapor deposited thin intermediate layer, and a metal-coated functional element having the aforementioned features.
Journal of Physics: Conference Series, 2006
This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It wi... more This paper is a brief report of plasma etching as applied to pattern transfer in silicon.
It will focus more on concept overview and strategies for etching of tapered features of interest
for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching
technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An
important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma
etch process is extremely sensitive to many variables such as mask material, mask openings
and more important the plasma parameters.
IEEE Transactions on Advanced Packaging, 2010
Through-Silicon-Via (TSV) interconnects using the "Via-Last" approach are successfully applied fo... more Through-Silicon-Via (TSV) interconnects using the "Via-Last" approach are successfully applied for wafer level packaging of CMOS image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer level packaging process for optical and M(O)EMS devices.
The present invention relates to a method for producing a firmly adhering metal-coated functional... more The present invention relates to a method for producing a firmly adhering metal-coated functional element comprising a base body and a coated thereon a metal coating, said metal coating is applied directly on the base body, but to a one acrylonitrile-containing gas before on the base body by means of a plasma polymerisation or vapor deposited thin intermediate layer, and a metal-coated functional element having the aforementioned features.
Journal of Physics: Conference Series, 2006
This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It wi... more This paper is a brief report of plasma etching as applied to pattern transfer in silicon.
It will focus more on concept overview and strategies for etching of tapered features of interest
for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching
technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An
important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma
etch process is extremely sensitive to many variables such as mask material, mask openings
and more important the plasma parameters.
IEEE Transactions on Advanced Packaging, 2010
Through-Silicon-Via (TSV) interconnects using the "Via-Last" approach are successfully applied fo... more Through-Silicon-Via (TSV) interconnects using the "Via-Last" approach are successfully applied for wafer level packaging of CMOS image sensors. Standard materials and processes are applied for redistribution on the backside of the devices, which is enabled by the use of plasma etched vias with tapered sidewalls. With this, high reliability for the packaged devices are achieved on component and board level. Based on the high uniformity for the via geometry in respect to the dimension of top opening, bottom opening and sidewall angle, we discuss the coverage of those redistribution polymers and photo resists as the bases for high performance and high yield of the mature wafer level packaging process for optical and M(O)EMS devices.