aakash tyagi | Indian Institute of Planning and Management (original) (raw)

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Papers by aakash tyagi

IEEE Transactions on Semiconductor Manufacturing, 1992

It is shown that generalized double Poisson distributions provide a good basis for yield models w... more It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported

A systolic array architecture for image segmentation by a split and merge procedure is proposed. ... more A systolic array architecture for image segmentation by a split and merge procedure is proposed. This architecture enhances the I/O and memory bandwidth requirements, which leads to speeding up the computation time of the segmentation of an image. The system structure is defined in terms of its interconnections and host computer interface along with other structural and behavioral considerations. Image segmentation through the proposed approach can be achieved in linear time

Yield enhancement may well be regarded as the quintessential objective in microelectronic manufac... more Yield enhancement may well be regarded as the quintessential objective in microelectronic manufacturing. With diminishing feature size and increasing die area the amount of functional silicon on a die is too expensive to discard in the event of short-circuit and open-circuit faults. Designing chips with high tolerance against faults, therefore, holds a great promise for profitable manufacturing in the semiconductor industry. In this paper we propose a post-processing defect-tolerant routing algorithm that reduces or eliminates short-circuit sensitive area, and minimizes vias in a two-layer channel routing solution. The algorithm is built to be sensitive to manufacturer's defect pareto figures. This feature gives the designer the flexibility of customizing the routing algorithm to the desired defect-tolerant features without increasing the die area or interconnect length

IEEE Transactions on Reliability, 1994

... 43, NO. 1, 1994 MARCH The Nature of Defect Patterns on Integrated-Circuit Wafer Maps Aakash T... more ... 43, NO. 1, 1994 MARCH The Nature of Defect Patterns on Integrated-Circuit Wafer Maps Aakash Tyagi, Member IEEE Magdy A. Bayoumi, Senior Member IEEE University of Southwestern Louisiana, Lafayette University of Southwestern Louisiana, Lafayette ...

IEEE Transactions on Signal Processing, 1992

An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is... more An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms