Sandeep K Shukla | IIT Kanpur (original) (raw)

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Papers by Sandeep K Shukla

Abstract In this paper we introduce an agile formal method (named XFM) based on extreme programmi... more Abstract In this paper we introduce an agile formal method (named XFM) based on extreme programming concepts to construct abstract models from a natural language specification of a complex system.

Abstract In this paper we show that stochastic learning automata based feedback control switching... more Abstract In this paper we show that stochastic learning automata based feedback control switching strategy can be used for dynamic power management (DPM) employed at the system level. DPM strategies are usually incorporated at the operating systems of embedded devices to exploit multiple power states available in today's ACPI compliant devices.

Emerging multicore architectures, especially Chip Multi-Processors (CMPs) and Multiprocessor Syst... more Emerging multicore architectures, especially Chip Multi-Processors (CMPs) and Multiprocessor Systems-on-Chip (MPSoC), are used in a wide variety of systems. They are necessary to avoid the unsustainable power consumption profile of increasing clock speed of uniprocessors in the early part of the last decade. The designers are thus forced to employ innovative design alternatives such as heterogeneous cores, novel network-on-chips, GPUs, and reconfigurable fabrics.

Abstract The increasing complexity and size of system level design models introduces a difficult ... more Abstract The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. In efforts to alleviate this problem, the authors propose a methodology of using structural reflection to extract structural information from design sources allowing the use of tools such as test bench generators and model viewers to seamlessly employ this extracted information.

Introduction of multi-core processors is one of the most significant changes in the semiconductor... more Introduction of multi-core processors is one of the most significant changes in the semiconductor industry in recent years. The shift to multi-core technology was preceded by a brief stint with the use of multiple virtual processors on top of a uniprocessor machine. Virtual processor techniques like the Intel Hyper-Threading technology [5] depended heavily on the distribution of computation between virtual processes.

Abstract Manufacturing and transient faults may be abundant in high density reconfigurable design... more Abstract Manufacturing and transient faults may be abundant in high density reconfigurable design fabrics as we move from deep submicron to nano-scale technologies. Design of reliable digital logic and architectures on such defective fabrics will require adequate redundancy. However, analysis of redundancy/reliability trade-offs for such designs will be required for micro-architects to do design space explorations.

Abstract In the recent years, Phasor Measurement Unit (PMU) based Wide Area Measurement System (W... more Abstract In the recent years, Phasor Measurement Unit (PMU) based Wide Area Measurement System (WAMS) has been receiving ever increasing attention from the academia as well as from the industry. Power utilities have been designing and implementing WAMS to provide more intelligent monitoring, control, and protection of the power grid.

Abstract SystemC's growing community for system-level design exploration is a result of SystemC's... more Abstract SystemC's growing community for system-level design exploration is a result of SystemC's capability of modeling at register transfer level (RTL) and above RTL abstraction levels. However, a synthesis path from SystemC at abstraction layers above RTL is still in its infancy. A recent extension of SystemC, which is called Bluespec-SystemC electronic system level (BS-ESL), counters this difficulty with its model of computation employing atomic rule-based specifications and synthesis to Verilog.

Abstract Majority gates play an important role in defect-and fault-tolerant circuit implementatio... more Abstract Majority gates play an important role in defect-and fault-tolerant circuit implementations for nanotechnologies due to their use in redundancy mechanisms such as TMR, CTMR etc. Therefore, providing reliable implementation of majority logic using some redundancy mechanism is extremely important.

Abstract Composing synchronous intellectual property (IP) blocks over asynchronous communication ... more Abstract Composing synchronous intellectual property (IP) blocks over asynchronous communication links for an system-on-chip (SoC) design is a challenging task, especially for ensuring the functional correctness of the overall design. In this paper, we propose a trace based framework to assist in validation of globally asynchronous locally synchronous (GALS) designs.

Abstract--Continuing advances in microelectronics technology and telecommunications have led to e... more Abstract--Continuing advances in microelectronics technology and telecommunications have led to emergence of highly networked embedded systems that contain interesting wireline and wireless interfaces along with substantial processing on the same board or chip. A typical``antenna-to-network" chip would incorporate a RF front end, baseband digital signal processing, link layer coding and medium access control functions along with applicationspecific processing.

Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provi... more Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provide geographically-dispersed operators with the ability to interact with the collected information and to control remote actuators. These devices are useful in a range of DRE application domains such as avionics, biomedical devices and telemedicine, remote sensing, space exploration and command and control.

ABSTRACT Bounded Model Checking (BMC) is often able to handle thousands of system variables by en... more ABSTRACT Bounded Model Checking (BMC) is often able to handle thousands of system variables by encoding the system and its properties via symbolic formulas and using satisfiability (SAT) solvers for verification. To further ease the verification of state invariants, BMC is augmented with a general induction rule called k-induction; however, this sacrifices completeness. Invariant strengthening, a method proposed to overcome this problem, often requires user intervention which limits its general applicability.

Abstract With the increased investment and deployment of embedded computing and communication tec... more Abstract With the increased investment and deployment of embedded computing and communication technologies in the power system���the smart grid vision is shaping up into a reality. The future power grid is a large cyber physical system (CPS) which is vulnerable to cyber security threats. Among the three major subsystems of a power grid���generation, transmission and distribution���this survey focuses on the transmission subsystem because most of the cyberization of the grid has been happening in this subsystem.

Abstract It is anticipated that self assembled ultra-dense nanomemories will be more susceptible ... more Abstract It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus the need exists for fault-tolerant memory architectures. The development of such architectures will require intense analysis in terms of achievable performance measures-power dissipation, area, delay and reliability.

Abstract Multi-clocked synchronous (aka Polychronous) specification languages do not assume that ... more Abstract Multi-clocked synchronous (aka Polychronous) specification languages do not assume that execution proceeds by sampling inputs at predetermined global synchronization points. The software synthesized from such specifications are paced by arrival of certain inputs, or evaluation of certain internal variables. Here, we present an alternate polychronous model of computation termed Multi-rate Instantaneous Channel connected Data Flow (MRICDF) actor network model.

Abstract Nanotechnology is a��� bottom-up��� engineering practice in which designers take individ... more Abstract Nanotechnology is a��� bottom-up��� engineering practice in which designers take individual atoms and assemble them into useful structures. Device manufacturing at such scales will be characterized by high defect rate. System architects will have to design defect tolerant reliable architectures to circumvent such defects. Due to the miniaturization of devices and the resulting increase in the device density, redundancy based architectures will gain importance.

Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous ... more Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to implement LIPs on long interconnects stems from the fact that with increasing clock frequencies, the signal delay on some interconnects exceeds the clock period.

Abstract In this paper we introduce an agile formal method (named XFM) based on extreme programmi... more Abstract In this paper we introduce an agile formal method (named XFM) based on extreme programming concepts to construct abstract models from a natural language specification of a complex system.

Abstract In this paper we show that stochastic learning automata based feedback control switching... more Abstract In this paper we show that stochastic learning automata based feedback control switching strategy can be used for dynamic power management (DPM) employed at the system level. DPM strategies are usually incorporated at the operating systems of embedded devices to exploit multiple power states available in today's ACPI compliant devices.

Emerging multicore architectures, especially Chip Multi-Processors (CMPs) and Multiprocessor Syst... more Emerging multicore architectures, especially Chip Multi-Processors (CMPs) and Multiprocessor Systems-on-Chip (MPSoC), are used in a wide variety of systems. They are necessary to avoid the unsustainable power consumption profile of increasing clock speed of uniprocessors in the early part of the last decade. The designers are thus forced to employ innovative design alternatives such as heterogeneous cores, novel network-on-chips, GPUs, and reconfigurable fabrics.

Abstract The increasing complexity and size of system level design models introduces a difficult ... more Abstract The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. In efforts to alleviate this problem, the authors propose a methodology of using structural reflection to extract structural information from design sources allowing the use of tools such as test bench generators and model viewers to seamlessly employ this extracted information.

Introduction of multi-core processors is one of the most significant changes in the semiconductor... more Introduction of multi-core processors is one of the most significant changes in the semiconductor industry in recent years. The shift to multi-core technology was preceded by a brief stint with the use of multiple virtual processors on top of a uniprocessor machine. Virtual processor techniques like the Intel Hyper-Threading technology [5] depended heavily on the distribution of computation between virtual processes.

Abstract Manufacturing and transient faults may be abundant in high density reconfigurable design... more Abstract Manufacturing and transient faults may be abundant in high density reconfigurable design fabrics as we move from deep submicron to nano-scale technologies. Design of reliable digital logic and architectures on such defective fabrics will require adequate redundancy. However, analysis of redundancy/reliability trade-offs for such designs will be required for micro-architects to do design space explorations.

Abstract In the recent years, Phasor Measurement Unit (PMU) based Wide Area Measurement System (W... more Abstract In the recent years, Phasor Measurement Unit (PMU) based Wide Area Measurement System (WAMS) has been receiving ever increasing attention from the academia as well as from the industry. Power utilities have been designing and implementing WAMS to provide more intelligent monitoring, control, and protection of the power grid.

Abstract SystemC's growing community for system-level design exploration is a result of SystemC's... more Abstract SystemC's growing community for system-level design exploration is a result of SystemC's capability of modeling at register transfer level (RTL) and above RTL abstraction levels. However, a synthesis path from SystemC at abstraction layers above RTL is still in its infancy. A recent extension of SystemC, which is called Bluespec-SystemC electronic system level (BS-ESL), counters this difficulty with its model of computation employing atomic rule-based specifications and synthesis to Verilog.

Abstract Majority gates play an important role in defect-and fault-tolerant circuit implementatio... more Abstract Majority gates play an important role in defect-and fault-tolerant circuit implementations for nanotechnologies due to their use in redundancy mechanisms such as TMR, CTMR etc. Therefore, providing reliable implementation of majority logic using some redundancy mechanism is extremely important.

Abstract Composing synchronous intellectual property (IP) blocks over asynchronous communication ... more Abstract Composing synchronous intellectual property (IP) blocks over asynchronous communication links for an system-on-chip (SoC) design is a challenging task, especially for ensuring the functional correctness of the overall design. In this paper, we propose a trace based framework to assist in validation of globally asynchronous locally synchronous (GALS) designs.

Abstract--Continuing advances in microelectronics technology and telecommunications have led to e... more Abstract--Continuing advances in microelectronics technology and telecommunications have led to emergence of highly networked embedded systems that contain interesting wireline and wireless interfaces along with substantial processing on the same board or chip. A typical``antenna-to-network" chip would incorporate a RF front end, baseband digital signal processing, link layer coding and medium access control functions along with applicationspecific processing.

Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provi... more Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provide geographically-dispersed operators with the ability to interact with the collected information and to control remote actuators. These devices are useful in a range of DRE application domains such as avionics, biomedical devices and telemedicine, remote sensing, space exploration and command and control.

ABSTRACT Bounded Model Checking (BMC) is often able to handle thousands of system variables by en... more ABSTRACT Bounded Model Checking (BMC) is often able to handle thousands of system variables by encoding the system and its properties via symbolic formulas and using satisfiability (SAT) solvers for verification. To further ease the verification of state invariants, BMC is augmented with a general induction rule called k-induction; however, this sacrifices completeness. Invariant strengthening, a method proposed to overcome this problem, often requires user intervention which limits its general applicability.

Abstract With the increased investment and deployment of embedded computing and communication tec... more Abstract With the increased investment and deployment of embedded computing and communication technologies in the power system���the smart grid vision is shaping up into a reality. The future power grid is a large cyber physical system (CPS) which is vulnerable to cyber security threats. Among the three major subsystems of a power grid���generation, transmission and distribution���this survey focuses on the transmission subsystem because most of the cyberization of the grid has been happening in this subsystem.

Abstract It is anticipated that self assembled ultra-dense nanomemories will be more susceptible ... more Abstract It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus the need exists for fault-tolerant memory architectures. The development of such architectures will require intense analysis in terms of achievable performance measures-power dissipation, area, delay and reliability.

Abstract Multi-clocked synchronous (aka Polychronous) specification languages do not assume that ... more Abstract Multi-clocked synchronous (aka Polychronous) specification languages do not assume that execution proceeds by sampling inputs at predetermined global synchronization points. The software synthesized from such specifications are paced by arrival of certain inputs, or evaluation of certain internal variables. Here, we present an alternate polychronous model of computation termed Multi-rate Instantaneous Channel connected Data Flow (MRICDF) actor network model.

Abstract Nanotechnology is a��� bottom-up��� engineering practice in which designers take individ... more Abstract Nanotechnology is a��� bottom-up��� engineering practice in which designers take individual atoms and assemble them into useful structures. Device manufacturing at such scales will be characterized by high defect rate. System architects will have to design defect tolerant reliable architectures to circumvent such defects. Due to the miniaturization of devices and the resulting increase in the device density, redundancy based architectures will gain importance.

Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous ... more Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to implement LIPs on long interconnects stems from the fact that with increasing clock frequencies, the signal delay on some interconnects exceeds the clock period.