Sudeb Dasgupta | IIT Roorkee (original) (raw)

Papers by Sudeb Dasgupta

Research paper thumbnail of Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

Microelectronics Journal, 2006

A two-dimensional numerical solution of electrostatic potential and electric field profiles are p... more A two-dimensional numerical solution of electrostatic potential and electric field profiles are presented for lightly doped nano-scale Double-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistor (DG-MOSFET). We have developed quasi-static (QS) model for evaluating bulk and inversion charges based on symmetric linearization model. We have also shown the non-quasi-static (NQS) effect on the charge due to a time varying gate voltage. It is seen that various symmetries of DG-MOSFET characteristics with respect to source/drain interchange is maintained in quasi-static as well as non-quasi-static version of the symmetrically linearized model. The variation of the threshold voltage with the varying width of the device is evaluated and presented. The results have been compared and contrasted with reported analytical model for QS condition for the purpose of verification of the model. The variation of threshold voltage along the width of the device is also predicted. This numerical model can be extended to analyze the transport phenomenon in sub 30 nm channel length DG-MOSFETs. q

Research paper thumbnail of Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

IEEE Transactions on Electron Devices, 2010

Digital circuits operating in a subthreshold region have gained wide interest due to their suitab... more Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS.

Research paper thumbnail of Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Vlsi Design, 2009

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power cons... more In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Research paper thumbnail of Guaranteed QoS With MIMO Systems for Scalable Low Motion Video Streaming Over Scarce Resource Wireless Channels

Information Processing, Jan 1, 2008

LM Patnaik and Venugopal KR (Eds.), ICIP-2008, Pages 452-466 © IK International Publishing House ... more LM Patnaik and Venugopal KR (Eds.), ICIP-2008, Pages 452-466 © IK International Publishing House Pvt. Ltd., New Delhi, India CHAPTER # $ Guaranteed QoS with MIMO Systems for Scalable Low Motion Video Streaming Over Scarce Resource Wireless Channels Saket Gupta1, ...

Research paper thumbnail of Modeling of Leakages In Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design

… Conference on VLSI …, Jan 1, 2007

... Low Power SRAM: A Device/Circuit Co-Design Deblina Sarkar 1 , Student Member, IEEE, Samiran G... more ... Low Power SRAM: A Device/Circuit Co-Design Deblina Sarkar 1 , Student Member, IEEE, Samiran Ganguly 1 , Student Member, IEEE, Deepanjan Datta 1 , Student Member, IEEE, AAP Sarab 1 and Sudeb Dasgupta 2 , Member, IEEE ...

Research paper thumbnail of MIMO Systems for Ensuring Multimedia QOS Over Scarce Resource Wireless Networks

Research paper thumbnail of Nanoscale Device Architecture to Reduce Leakage Currents Through Quantum-Mechanical Simulation

… of Vacuum Science & Technology B: …, Jan 1, 2006

In this article, the effect of the gate tunneling current in ultrathin gate-oxide metal-oxide-sem... more In this article, the effect of the gate tunneling current in ultrathin gate-oxide metal-oxide-semiconductor (MOS) devices of an effective gate length of is studied using a device simulation. A dramatic increase of gate and reverse-biased junction band-to-band-tunneling leakages in scaled ...

Research paper thumbnail of A 1.2 Volt, 90nm, 16-Bit Three Way Segmented Digital to Analog Converter (DAC) for Low Power Applications

ieeexplore.ieee.org

Abstract This paper presents a new scheme of designing a 16-bit Digital to Analog Converter with ... more Abstract This paper presents a new scheme of designing a 16-bit Digital to Analog Converter with a Supply voltage of 1.2 Volts. The proposed design combines three different architectures in a novel way so as to achieve low power and low area requirements of the present day ...

Research paper thumbnail of Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

Microelectronics Journal, 2006

A two-dimensional numerical solution of electrostatic potential and electric field profiles are p... more A two-dimensional numerical solution of electrostatic potential and electric field profiles are presented for lightly doped nano-scale Double-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistor (DG-MOSFET). We have developed quasi-static (QS) model for evaluating bulk and inversion charges based on symmetric linearization model. We have also shown the non-quasi-static (NQS) effect on the charge due to a time varying gate voltage. It is seen that various symmetries of DG-MOSFET characteristics with respect to source/drain interchange is maintained in quasi-static as well as non-quasi-static version of the symmetrically linearized model. The variation of the threshold voltage with the varying width of the device is evaluated and presented. The results have been compared and contrasted with reported analytical model for QS condition for the purpose of verification of the model. The variation of threshold voltage along the width of the device is also predicted. This numerical model can be extended to analyze the transport phenomenon in sub 30 nm channel length DG-MOSFETs. q

Research paper thumbnail of Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

IEEE Transactions on Electron Devices, 2010

Digital circuits operating in a subthreshold region have gained wide interest due to their suitab... more Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS.

Research paper thumbnail of Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Vlsi Design, 2009

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power cons... more In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Research paper thumbnail of Guaranteed QoS With MIMO Systems for Scalable Low Motion Video Streaming Over Scarce Resource Wireless Channels

Information Processing, Jan 1, 2008

LM Patnaik and Venugopal KR (Eds.), ICIP-2008, Pages 452-466 © IK International Publishing House ... more LM Patnaik and Venugopal KR (Eds.), ICIP-2008, Pages 452-466 © IK International Publishing House Pvt. Ltd., New Delhi, India CHAPTER # $ Guaranteed QoS with MIMO Systems for Scalable Low Motion Video Streaming Over Scarce Resource Wireless Channels Saket Gupta1, ...

Research paper thumbnail of Modeling of Leakages In Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design

… Conference on VLSI …, Jan 1, 2007

... Low Power SRAM: A Device/Circuit Co-Design Deblina Sarkar 1 , Student Member, IEEE, Samiran G... more ... Low Power SRAM: A Device/Circuit Co-Design Deblina Sarkar 1 , Student Member, IEEE, Samiran Ganguly 1 , Student Member, IEEE, Deepanjan Datta 1 , Student Member, IEEE, AAP Sarab 1 and Sudeb Dasgupta 2 , Member, IEEE ...

Research paper thumbnail of MIMO Systems for Ensuring Multimedia QOS Over Scarce Resource Wireless Networks

Research paper thumbnail of Nanoscale Device Architecture to Reduce Leakage Currents Through Quantum-Mechanical Simulation

… of Vacuum Science & Technology B: …, Jan 1, 2006

In this article, the effect of the gate tunneling current in ultrathin gate-oxide metal-oxide-sem... more In this article, the effect of the gate tunneling current in ultrathin gate-oxide metal-oxide-semiconductor (MOS) devices of an effective gate length of is studied using a device simulation. A dramatic increase of gate and reverse-biased junction band-to-band-tunneling leakages in scaled ...

Research paper thumbnail of A 1.2 Volt, 90nm, 16-Bit Three Way Segmented Digital to Analog Converter (DAC) for Low Power Applications

ieeexplore.ieee.org

Abstract This paper presents a new scheme of designing a 16-bit Digital to Analog Converter with ... more Abstract This paper presents a new scheme of designing a 16-bit Digital to Analog Converter with a Supply voltage of 1.2 Volts. The proposed design combines three different architectures in a novel way so as to achieve low power and low area requirements of the present day ...