Christos Papavassiliou | Imperial College London (original) (raw)

Uploads

Papers by Christos Papavassiliou

Medical & Biological Engineering & Computing

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Memristors show great potential for being integrated into CMOS technology and provide new approac... more Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state 1 switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multistate memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multistate memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

IEEE Power Engineering Review, 1983

arXiv (Cornell University), Sep 21, 2020

Recording reliably extracellular neural activities is an essential prerequisite for the developme... more Recording reliably extracellular neural activities is an essential prerequisite for the development of bioelectronics and neuroprosthetic applications. Recently, a fully differential, 2-stage, integrating pre-amplifier was proposed for amplifying and then digitising neural signals. The amplifier featured a finely tuneable offset that was used as a variable threshold detector. Given that the amplifier is integrating, the DC operating point keeps changing during integration, rendering traditional analysis (AC/DC) unsuitable. In this work, we analyse the operation of this circuit and propose alternative definitions for validating the necessary key performance metrics, including: gain, bandwidth, offset tuning range and offset sensitivity with respect to the memory states of the employed memristors. The amplification process is analysed largely through investigating the transient behaviour during the integration phase. This benchmarking approach is finally leveraged for providing useful insights and design trade-offs of the memristor-based integrating amplifier.

ABSTRACT A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic... more ABSTRACT A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.

ACS applied electronic materials, Feb 15, 2023

IEEE Transactions on Electron Devices, Jul 1, 2015

Selectorless crossbar arrays of resistive randomaccess memory (RRAM), also known as memristors, c... more Selectorless crossbar arrays of resistive randomaccess memory (RRAM), also known as memristors, conduct large sneak currents during operation, which can significantly corrupt the accuracy of cross-point analog resistance (M t) measurements. In order to mitigate this issue, we have designed, built, and tested a memristor characterization and testing (mCAT) instrument that forces redistribution of sneak currents within the crossbar array, dramatically increasing M t measurement accuracy. We calibrated the mCAT using a custom-made 32 × 32 discrete resistive crossbar array, and subsequently demonstrated its functionality on solid-state TiO 2−x RRAM arrays, on wafer and packaged, of the same size. Our platform can measure standalone M t in the range of 1 k to 1 M with <1% error. For our custom resistive crossbar, 90% of devices of the same resistance range were measured with <10% error. The platform's limitations have been quantified using large-scale nonideal crossbar simulations.

IEEE Transactions on Circuits and Systems Ii-express Briefs, 2005

This brief presents a new topology of a multibit quadrature band-pass sigma-delta modulator which... more This brief presents a new topology of a multibit quadrature band-pass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor (SC) implementations by using the same capacitors to sample the input and the reference of the feedback DACs. Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex band-pass case is proposed for the case of multibit feedback DACs.

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 24, 2022

This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator ... more This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator using a memristive finite impulse response (FIR) digital-to-analog converter (DAC) in the feedback. To achieve better power and circuit area efficiency, the coefficients of the 8-tap FIR filter are implemented using memristors with programmable resistance in the range of 17.20k to 55.63k. The modulator was designed and simulated using a 180nm standard CMOS technology in addition to a memristor model, which was constructed based on the measured characteristics of the real device behavior. The modulator targets 10kHz signal bandwidth and samples at 10MHz. Simulation results show that the FIR DAC can improve the modulator signal-to-noise and distortion ratio (SNDR) from 44.36dB to 62.29dB with the existence of 5ns RMS jitter at the sampling clock. The FIR DAC still contributes to a better modulator SNDR performance even considering a worst-case 20% resistance variation of the memristors.

Medical & Biological Engineering & Computing, Sep 17, 2022

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

IEEE Transactions on Circuits and Systems I: Regular Papers

2022 International Conference on Microelectronics (ICM), Dec 4, 2022

2022 International Conference on Microelectronics (ICM)

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Mass characterisation of emerging memory devices is an essential step in modelling their behaviou... more Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20 nA to 2 mA). This allows a device's resistance range to be between 1 kΩ and 10 MΩ with a minimum voltage range of ±1.5 V on the device.

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Medical & Biological Engineering & Computing

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Memristors show great potential for being integrated into CMOS technology and provide new approac... more Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state 1 switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multistate memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multistate memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

IEEE Power Engineering Review, 1983

arXiv (Cornell University), Sep 21, 2020

Recording reliably extracellular neural activities is an essential prerequisite for the developme... more Recording reliably extracellular neural activities is an essential prerequisite for the development of bioelectronics and neuroprosthetic applications. Recently, a fully differential, 2-stage, integrating pre-amplifier was proposed for amplifying and then digitising neural signals. The amplifier featured a finely tuneable offset that was used as a variable threshold detector. Given that the amplifier is integrating, the DC operating point keeps changing during integration, rendering traditional analysis (AC/DC) unsuitable. In this work, we analyse the operation of this circuit and propose alternative definitions for validating the necessary key performance metrics, including: gain, bandwidth, offset tuning range and offset sensitivity with respect to the memory states of the employed memristors. The amplification process is analysed largely through investigating the transient behaviour during the integration phase. This benchmarking approach is finally leveraged for providing useful insights and design trade-offs of the memristor-based integrating amplifier.

ABSTRACT A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic... more ABSTRACT A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.

ACS applied electronic materials, Feb 15, 2023

IEEE Transactions on Electron Devices, Jul 1, 2015

Selectorless crossbar arrays of resistive randomaccess memory (RRAM), also known as memristors, c... more Selectorless crossbar arrays of resistive randomaccess memory (RRAM), also known as memristors, conduct large sneak currents during operation, which can significantly corrupt the accuracy of cross-point analog resistance (M t) measurements. In order to mitigate this issue, we have designed, built, and tested a memristor characterization and testing (mCAT) instrument that forces redistribution of sneak currents within the crossbar array, dramatically increasing M t measurement accuracy. We calibrated the mCAT using a custom-made 32 × 32 discrete resistive crossbar array, and subsequently demonstrated its functionality on solid-state TiO 2−x RRAM arrays, on wafer and packaged, of the same size. Our platform can measure standalone M t in the range of 1 k to 1 M with <1% error. For our custom resistive crossbar, 90% of devices of the same resistance range were measured with <10% error. The platform's limitations have been quantified using large-scale nonideal crossbar simulations.

IEEE Transactions on Circuits and Systems Ii-express Briefs, 2005

This brief presents a new topology of a multibit quadrature band-pass sigma-delta modulator which... more This brief presents a new topology of a multibit quadrature band-pass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor (SC) implementations by using the same capacitors to sample the input and the reference of the feedback DACs. Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex band-pass case is proposed for the case of multibit feedback DACs.

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 24, 2022

This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator ... more This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator using a memristive finite impulse response (FIR) digital-to-analog converter (DAC) in the feedback. To achieve better power and circuit area efficiency, the coefficients of the 8-tap FIR filter are implemented using memristors with programmable resistance in the range of 17.20k to 55.63k. The modulator was designed and simulated using a 180nm standard CMOS technology in addition to a memristor model, which was constructed based on the measured characteristics of the real device behavior. The modulator targets 10kHz signal bandwidth and samples at 10MHz. Simulation results show that the FIR DAC can improve the modulator signal-to-noise and distortion ratio (SNDR) from 44.36dB to 62.29dB with the existence of 5ns RMS jitter at the sampling clock. The FIR DAC still contributes to a better modulator SNDR performance even considering a worst-case 20% resistance variation of the memristors.

Medical & Biological Engineering & Computing, Sep 17, 2022

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

IEEE Transactions on Circuits and Systems I: Regular Papers

2022 International Conference on Microelectronics (ICM), Dec 4, 2022

2022 International Conference on Microelectronics (ICM)

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Mass characterisation of emerging memory devices is an essential step in modelling their behaviou... more Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20 nA to 2 mA). This allows a device's resistance range to be between 1 kΩ and 10 MΩ with a minimum voltage range of ±1.5 V on the device.

2022 IEEE International Symposium on Circuits and Systems (ISCAS)