Georgi Gaydadjiev | Imperial College London (original) (raw)

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Papers by Georgi Gaydadjiev

Research paper thumbnail of The midlifekicker microarchitecture evaluation metric

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Research paper thumbnail of 2 Guest Editors’ Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarro 5 ArchExplorer for Automatic Design Space Exploration

2 Guest Editors' Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarr... more 2 Guest Editors' Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarro ... 5 ArchExplorer for Automatic Design Space Exploration Veerle Desmet, Sylvain Girbal, Alex Ramirez, Augusto Vega, and Olivier Temam ... 16 The SARC Architecture Alex Ramirez, Felipe Cabarcas, Ben Juurlink, Mauricio Alvarez Mesa, Friman Sanchez, Arnaldo Azevedo, Cor Meenderinck, Ca˘ta˘lin Ciobanu, Sebastian Isaza, and Georgi Gaydadjiev ... 30 Explicit Communication and Synchronization in SARC Manolis GH Katevenis, Vassilis Papaefstathiou, Stamatis ...

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Research paper thumbnail of Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

2009 International Conference on Complex, Intelligent and Software Intensive Systems, 2009

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Research paper thumbnail of Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

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Research paper thumbnail of Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

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Research paper thumbnail of Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

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Research paper thumbnail of DeSyRe: On-demand system reliability

Microprocessors and Microsystems, 2013

ABSTRACT The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fa... more ABSTRACT The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints.

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Research paper thumbnail of 1293 On Implementability Of Polymorphic Register Files

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Research paper thumbnail of 1320 Implementation Study Of Fft On Multilane Vector Processors

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Research paper thumbnail of Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory

2014 43rd International Conference on Parallel Processing, 2014

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Research paper thumbnail of Exploiting SPMD Horizontal Locality

IEEE Computer Architecture Letters, 2011

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Research paper thumbnail of General Purpose Computing with Reconfigurable Acceleration

2010 International Conference on Field Programmable Logic and Applications, 2010

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Research paper thumbnail of Range Trees with variable length comparisons

2009 International Conference on High Performance Switching and Routing, 2009

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Research paper thumbnail of Elastic pipeline

Proceedings of the 8th ACM International Conference on Computing Frontiers - CF '11, 2011

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Research paper thumbnail of A Platform for RFID Security and Privacy Administration

USENIX Systems Administration Conference, 2000

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Research paper thumbnail of HiPEAC: Upcoming Challenges in Reconfigurable Computing

Reconfigurable Computing, 2011

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Research paper thumbnail of Challenges for embedded multicore architecture

Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems - CASES '10, 2010

ABSTRACT

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Research paper thumbnail of Compiler-aided methodology for low overhead on-line testing

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013

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Research paper thumbnail of Using a CISC microcontroller to test embedded memories

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

ABSTRACT

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Research paper thumbnail of Low-cost, customized and flexible SRAM MBIST engine

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

ABSTRACT

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Research paper thumbnail of The midlifekicker microarchitecture evaluation metric

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Research paper thumbnail of 2 Guest Editors’ Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarro 5 ArchExplorer for Automatic Design Space Exploration

2 Guest Editors' Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarr... more 2 Guest Editors' Introduction: Multicore: The View from Europe Mateo Valero and Nacho Navarro ... 5 ArchExplorer for Automatic Design Space Exploration Veerle Desmet, Sylvain Girbal, Alex Ramirez, Augusto Vega, and Olivier Temam ... 16 The SARC Architecture Alex Ramirez, Felipe Cabarcas, Ben Juurlink, Mauricio Alvarez Mesa, Friman Sanchez, Arnaldo Azevedo, Cor Meenderinck, Ca˘ta˘lin Ciobanu, Sebastian Isaza, and Georgi Gaydadjiev ... 30 Explicit Communication and Synchronization in SARC Manolis GH Katevenis, Vassilis Papaefstathiou, Stamatis ...

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Research paper thumbnail of Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

2009 International Conference on Complex, Intelligent and Software Intensive Systems, 2009

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

Bookmarks Related papers MentionsView impact

Research paper thumbnail of DeSyRe: On-demand system reliability

Microprocessors and Microsystems, 2013

ABSTRACT The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fa... more ABSTRACT The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints.

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Research paper thumbnail of 1293 On Implementability Of Polymorphic Register Files

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 1320 Implementation Study Of Fft On Multilane Vector Processors

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory

2014 43rd International Conference on Parallel Processing, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Exploiting SPMD Horizontal Locality

IEEE Computer Architecture Letters, 2011

Bookmarks Related papers MentionsView impact

Research paper thumbnail of General Purpose Computing with Reconfigurable Acceleration

2010 International Conference on Field Programmable Logic and Applications, 2010

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Range Trees with variable length comparisons

2009 International Conference on High Performance Switching and Routing, 2009

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Elastic pipeline

Proceedings of the 8th ACM International Conference on Computing Frontiers - CF '11, 2011

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A Platform for RFID Security and Privacy Administration

USENIX Systems Administration Conference, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of HiPEAC: Upcoming Challenges in Reconfigurable Computing

Reconfigurable Computing, 2011

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Challenges for embedded multicore architecture

Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems - CASES '10, 2010

ABSTRACT

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Compiler-aided methodology for low overhead on-line testing

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Using a CISC microcontroller to test embedded memories

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

ABSTRACT

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low-cost, customized and flexible SRAM MBIST engine

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

ABSTRACT

Bookmarks Related papers MentionsView impact