ANGEL VAZQUEZ - Academia.edu (original) (raw)

Papers by ANGEL VAZQUEZ

Research paper thumbnail of CMOS fully-differential bandpass modulator using switched-current circuits

Electronics Letters, 1996

This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fu... more This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0. 8~ CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation (Z-L-z-3 to a second-order lowpass EA modulator. Specifications are SNR260dB@2.5Mhz+15Khz, for a clock frequency of 1OMhz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5Mhz clock frequency.

Research paper thumbnail of Geometrically constrained parasitic-aware synthesis of analog ICs

SPIE Proceedings, 2005

In order to speed up the design process of analog ICs, iterations between different design stages... more In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very timeconsuming task: if circuit performance including layout-induced degradations proves unacceptable, a redesign cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layoutaware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.

Research paper thumbnail of Dimensionality reduction for EEG classification using Mutual Information and SVM MUTUAL INFORMATION AND SVM

Dimensionality reduction is a well known technique in signal processing oriented to improve both ... more Dimensionality reduction is a well known technique in signal processing oriented to improve both the computational cost and the performance of classifiers. We use an electroencephalogram (EEG) feature matrix based on three extraction methods: tracks extraction, wavelets coefficients and Fractional Fourier Transform. The dimension reduction is performed by Mutual Information (MI) and a forwardbackward procedure. Our results show that feature extraction and dimension reduction could be considered as a new alternative for solving EEG classification problems.

Research paper thumbnail of CMOS fully-differential bandpass modulator using switched-current circuits

Electronics Letters, 1996

This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fu... more This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0. 8~ CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation (Z-L-z-3 to a second-order lowpass EA modulator. Specifications are SNR260dB@2.5Mhz+15Khz, for a clock frequency of 1OMhz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5Mhz clock frequency.

Research paper thumbnail of Geometrically constrained parasitic-aware synthesis of analog ICs

SPIE Proceedings, 2005

In order to speed up the design process of analog ICs, iterations between different design stages... more In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very timeconsuming task: if circuit performance including layout-induced degradations proves unacceptable, a redesign cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layoutaware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.

Research paper thumbnail of Dimensionality reduction for EEG classification using Mutual Information and SVM MUTUAL INFORMATION AND SVM

Dimensionality reduction is a well known technique in signal processing oriented to improve both ... more Dimensionality reduction is a well known technique in signal processing oriented to improve both the computational cost and the performance of classifiers. We use an electroencephalogram (EEG) feature matrix based on three extraction methods: tracks extraction, wavelets coefficients and Fractional Fourier Transform. The dimension reduction is performed by Mutual Information (MI) and a forwardbackward procedure. Our results show that feature extraction and dimension reduction could be considered as a new alternative for solving EEG classification problems.