Abhoy Kole - Academia.edu (original) (raw)
Papers by Abhoy Kole
2020 IEEE International Test Conference India
Encoding of quantum information and carrying out computation on encoded state is an essential req... more Encoding of quantum information and carrying out computation on encoded state is an essential requirement for improving the reliability of a quantum computer. Resource limitation in today’s noisy intermediate scale quantum (NISQ) processors further restricts carrying out fault-tolerant quantum gate operations on such systems. Recent experiments conducted on physical qubits of superconducting transmon type and trapped atomic ions using the fault-tolerant scheme based on [[4, 2, 2]] code have shown a systematic improvement in the fidelity of all logical quantum gate operations except the logical controlled-NOT (CNOT) operation that requires 3 physical SWAP operations for fault-tolerant realization.In this present work we propose an optimal realization of logical CNOT operations on a single or two separate [[4, 2, 2]] code-words using 4 physical CNOT operations and an additional qubit. We further introduce logical two-qubit positive and negative controlled-phase operations with varying rotation angle, and also propose the fault-tolerant realization of logical 2-controlled-phase (C2Z)(C^{2}Z)(C2Z) and 2-controlled-NOT (C2 NOT) operations that are required for universal computation using [[4, 2, 2]] encoding. The implementation requires less number of encoded operations and one additional qubit. Through experiments conducted on the 15-qubit IBM Quantum Experience processor and QASM simulator the fidelity and validity of all these proposed gate operations have been verified.
2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017
The problem of synthesis and optimization of reversible and quantum circuits have drawn the atten... more The problem of synthesis and optimization of reversible and quantum circuits have drawn the attention of researchers in recent years. The typical design flow for such circuits first carries out the step of synthesis in terms of reversible gates, and then maps (decomposes) each reversible gate into equivalent set of quantum gates (e.g. from the NCV library). Since its initial proposal in realizing a Toffoli gate using quantum gates, several structural modifications have been proposed in the literature in order to reduce the cost of the generated netlist. The most recently introduced approach produces improved NCV cascade successively by partitioning the control lines of the given Toffoli gate in all possible ways, and replacing intermediate Toffoli gates with optimized equivalent NCV cascades form a catalog. In this approach the complexity of decomposing large Toffoli gates is high. In the present paper an efficient heuristic for partitioning the control lines of a given Toffoli gate...
Motivated by the prospects of quantum computation, the design of quantum circuits received signif... more Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit. This paper proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. Research works are mostly carried out considering nearest neighbor constraints at the quantum circuit level. Various quantum gate libraries and mapping schemes have been reported in the literature to realize the circuit operation at quantum level. One such mapping scheme exploiting a well established quantum gate library (NCV) is explored in defining the cost metric. Experimental evaluations confirmed both the accuracy as well as the applicability of the proposed metric.
Procedia Computer Science, 2016
Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis... more Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli + (N T ,T T ,T T +). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (N T ,T T ,T T +) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works.
This work in progress report proposes a new metric for estimating nearest neighbor cost at the re... more This work in progress report proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. This is in contrast to existing literature where nearest neighbor constraints are usually considered at the quantum circuit level. In order to define the metric, investigations on a state-of-the-art reversible to quantum mapping scheme have been conducted. From the retrieved information, a proper estimation to be used as a cost metric has been obtained. Using the metric, it becomes possible for the first time to optimize a reversible circuit with respect to nearest neighbor constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum computers are becoming a reality today due to the rapid progress made by researchers in t... more Quantum computers are becoming a reality today due to the rapid progress made by researchers in the last years. In the process of building quantum computers, IBM has developed several versions-starting from 5-qubit architectures like IBM QX2 and IBM QX4 to larger 16-or 20-qubit architectures. These architectures support arbitrary rotations of a single qubit and a controlled negation (CNOT) involving two qubits. The two qubit operations come with added coupling-map restrictions that only allow specific physical qubits to be the control and target qubits of the operation. In order to execute a quantum circuit on the IBM QX architecture, CNOT gates must satisfy the so-called coupling constraints of the architecture. Previous works addressed this issue with the objective of reducing the number of gates and the circuit depth. However, in this work we show that further improvements are possible. To this end, we present a general approach for further improving the number of gate operations and depth of the mapped circuit. The proposed approach encompasses the selection of physical qubits, determining initial and local permutations efficiently to obtain the final circuit mapped to the given IBM QX architecture. Through experiments improvements are observed over existing methods in terms of the number of gates and circuit depth.
Journal of The Institution of Engineers (India): Series B
Ternary reversible logic synthesis has started gaining the attention of researchers in recent yea... more Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multipolarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
One of the main challenges in quantum computing is to ensure error-free operation of the basic qu... more One of the main challenges in quantum computing is to ensure error-free operation of the basic quantum gates. There are various implementation technologies of quantum gates for which the distance between interacting qubits must be kept within a limit for reliable operation. This leads to the so-called requirement of neighborhood arrangements of the interacting qubits, often referred to as nearest neighbor (NN) constraint. This is typically achieved by inserting SWAP gates in the quantum circuits, where a SWAP gate between two qubits exchanges their states. Minimizing the number of SWAP gates to provide NN compliance is an important problem to solve. A number of approaches have been proposed in this regard, based on local and global ordering techniques. In this paper, a generalized approach for combined local and global ordering of qubits have been proposed that is based on an improved heuristic for cost estimation and is also scalable. The approach can be extended to <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula>-dimensional arrangement of qubits, for any arbitrary values of <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula>. Practical constraints, however, restrict the maximum value of <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> to 3. Extensive experiments on benchmark functions have been carried out to evaluate the performance in terms of SWAP gate requirements. 3-D organization of qubits shows average reductions of 6.7% and 37.4%, respectively, in the number of SWAP gates over 2-D and 1-D organizations. Also compared to the best 2-D and 1-D results reported in the literature, on the average 8.7% and 8.4% reductions, respectively, are observed.
Reversible Computation
With the development in quantum computing, nearest neighbor constraint has become important for c... more With the development in quantum computing, nearest neighbor constraint has become important for circuit realization. Various works have tried to make a circuit nearest neighbor compliant (NNC) by using minimum number of SWAP gates. To this end, an efficient qubit placement strategy is proposed that considers interaction among qubits and their positions of occurrence. Experimental results show that the proposed method reduces the number of SWAP gates by 3.3% to 36.1% on the average as compared to recently published works.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016
With recent interest in reversible and quantum computation, research in synthesis of reversible a... more With recent interest in reversible and quantum computation, research in synthesis of reversible and quantum circuits has increased in momentum. With additional requirements of neighborhood interactions among qubits (with two basis states) being a necessity in some physical realizations, several works on obtaining nearest neighbor quantum gate realization by inserting SWAP gates have been reported. These methods are based on two broad optimization approaches, one based on global ordering, where qubits are ordered over the whole netlist, and the other based on local ordering for minimizing SWAP gate insertions on smaller segments of netlists. Further reductions in cost are possible by using multi-valued qudits that have more than two basis states. The present paper considers a quantum circuit based on the NCV library, and proposes a better SWAP gate insertion method based on local ordering that uses an N-gate lookahead approach to reduce cost. Experimental results on benchmark circuits and comparison against published works confirm the benefits of the proposed approach, with improvements over reported works obtained in the range of 27%-43% on the average and 54%-63% in the best case. The method is also scalable for larger circuits, with the longest runtime observed as 10 minutes.
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)
Realization of logic functions using ternary reversible logic is known to requirelesser number of... more Realization of logic functions using ternary reversible logic is known to requirelesser number of lines as compared to conventionalbinary reversible logic. This aspect of ternary reversible logic has motivated researchers to explore various synthesis approaches in the past. Existing synthesis methods require additional lines (called ancilla lines)for synthesis, which is expensive from the quantum implementation pointof view. There is no reported work for ternary reversible logic synthesisthat require the minimum possible number of gates and also lines. Thisclass of synthesis methods is called exact synthesis. In this paper two exact synthesis methods for ternary reversible logic have been proposed for the first time, one based on booleansatisfiability (SAT) and the other based on level-constrained heuristic search technique. A permutation representing a reversible ternary truth table is given as input, and a reversible circuit consisting ofgeneralized ternary Toffoli gates that implements the permutationis obtained as output. Experimental studies have been carried out on various randomly generatedternary reversible functions.
2020 IEEE International Test Conference India
Encoding of quantum information and carrying out computation on encoded state is an essential req... more Encoding of quantum information and carrying out computation on encoded state is an essential requirement for improving the reliability of a quantum computer. Resource limitation in today’s noisy intermediate scale quantum (NISQ) processors further restricts carrying out fault-tolerant quantum gate operations on such systems. Recent experiments conducted on physical qubits of superconducting transmon type and trapped atomic ions using the fault-tolerant scheme based on [[4, 2, 2]] code have shown a systematic improvement in the fidelity of all logical quantum gate operations except the logical controlled-NOT (CNOT) operation that requires 3 physical SWAP operations for fault-tolerant realization.In this present work we propose an optimal realization of logical CNOT operations on a single or two separate [[4, 2, 2]] code-words using 4 physical CNOT operations and an additional qubit. We further introduce logical two-qubit positive and negative controlled-phase operations with varying rotation angle, and also propose the fault-tolerant realization of logical 2-controlled-phase (C2Z)(C^{2}Z)(C2Z) and 2-controlled-NOT (C2 NOT) operations that are required for universal computation using [[4, 2, 2]] encoding. The implementation requires less number of encoded operations and one additional qubit. Through experiments conducted on the 15-qubit IBM Quantum Experience processor and QASM simulator the fidelity and validity of all these proposed gate operations have been verified.
2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017
The problem of synthesis and optimization of reversible and quantum circuits have drawn the atten... more The problem of synthesis and optimization of reversible and quantum circuits have drawn the attention of researchers in recent years. The typical design flow for such circuits first carries out the step of synthesis in terms of reversible gates, and then maps (decomposes) each reversible gate into equivalent set of quantum gates (e.g. from the NCV library). Since its initial proposal in realizing a Toffoli gate using quantum gates, several structural modifications have been proposed in the literature in order to reduce the cost of the generated netlist. The most recently introduced approach produces improved NCV cascade successively by partitioning the control lines of the given Toffoli gate in all possible ways, and replacing intermediate Toffoli gates with optimized equivalent NCV cascades form a catalog. In this approach the complexity of decomposing large Toffoli gates is high. In the present paper an efficient heuristic for partitioning the control lines of a given Toffoli gate...
Motivated by the prospects of quantum computation, the design of quantum circuits received signif... more Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit. This paper proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. Research works are mostly carried out considering nearest neighbor constraints at the quantum circuit level. Various quantum gate libraries and mapping schemes have been reported in the literature to realize the circuit operation at quantum level. One such mapping scheme exploiting a well established quantum gate library (NCV) is explored in defining the cost metric. Experimental evaluations confirmed both the accuracy as well as the applicability of the proposed metric.
Procedia Computer Science, 2016
Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis... more Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli + (N T ,T T ,T T +). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (N T ,T T ,T T +) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works.
This work in progress report proposes a new metric for estimating nearest neighbor cost at the re... more This work in progress report proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. This is in contrast to existing literature where nearest neighbor constraints are usually considered at the quantum circuit level. In order to define the metric, investigations on a state-of-the-art reversible to quantum mapping scheme have been conducted. From the retrieved information, a proper estimation to be used as a cost metric has been obtained. Using the metric, it becomes possible for the first time to optimize a reversible circuit with respect to nearest neighbor constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum computers are becoming a reality today due to the rapid progress made by researchers in t... more Quantum computers are becoming a reality today due to the rapid progress made by researchers in the last years. In the process of building quantum computers, IBM has developed several versions-starting from 5-qubit architectures like IBM QX2 and IBM QX4 to larger 16-or 20-qubit architectures. These architectures support arbitrary rotations of a single qubit and a controlled negation (CNOT) involving two qubits. The two qubit operations come with added coupling-map restrictions that only allow specific physical qubits to be the control and target qubits of the operation. In order to execute a quantum circuit on the IBM QX architecture, CNOT gates must satisfy the so-called coupling constraints of the architecture. Previous works addressed this issue with the objective of reducing the number of gates and the circuit depth. However, in this work we show that further improvements are possible. To this end, we present a general approach for further improving the number of gate operations and depth of the mapped circuit. The proposed approach encompasses the selection of physical qubits, determining initial and local permutations efficiently to obtain the final circuit mapped to the given IBM QX architecture. Through experiments improvements are observed over existing methods in terms of the number of gates and circuit depth.
Journal of The Institution of Engineers (India): Series B
Ternary reversible logic synthesis has started gaining the attention of researchers in recent yea... more Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multipolarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
One of the main challenges in quantum computing is to ensure error-free operation of the basic qu... more One of the main challenges in quantum computing is to ensure error-free operation of the basic quantum gates. There are various implementation technologies of quantum gates for which the distance between interacting qubits must be kept within a limit for reliable operation. This leads to the so-called requirement of neighborhood arrangements of the interacting qubits, often referred to as nearest neighbor (NN) constraint. This is typically achieved by inserting SWAP gates in the quantum circuits, where a SWAP gate between two qubits exchanges their states. Minimizing the number of SWAP gates to provide NN compliance is an important problem to solve. A number of approaches have been proposed in this regard, based on local and global ordering techniques. In this paper, a generalized approach for combined local and global ordering of qubits have been proposed that is based on an improved heuristic for cost estimation and is also scalable. The approach can be extended to <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula>-dimensional arrangement of qubits, for any arbitrary values of <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula>. Practical constraints, however, restrict the maximum value of <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> to 3. Extensive experiments on benchmark functions have been carried out to evaluate the performance in terms of SWAP gate requirements. 3-D organization of qubits shows average reductions of 6.7% and 37.4%, respectively, in the number of SWAP gates over 2-D and 1-D organizations. Also compared to the best 2-D and 1-D results reported in the literature, on the average 8.7% and 8.4% reductions, respectively, are observed.
Reversible Computation
With the development in quantum computing, nearest neighbor constraint has become important for c... more With the development in quantum computing, nearest neighbor constraint has become important for circuit realization. Various works have tried to make a circuit nearest neighbor compliant (NNC) by using minimum number of SWAP gates. To this end, an efficient qubit placement strategy is proposed that considers interaction among qubits and their positions of occurrence. Experimental results show that the proposed method reduces the number of SWAP gates by 3.3% to 36.1% on the average as compared to recently published works.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016
With recent interest in reversible and quantum computation, research in synthesis of reversible a... more With recent interest in reversible and quantum computation, research in synthesis of reversible and quantum circuits has increased in momentum. With additional requirements of neighborhood interactions among qubits (with two basis states) being a necessity in some physical realizations, several works on obtaining nearest neighbor quantum gate realization by inserting SWAP gates have been reported. These methods are based on two broad optimization approaches, one based on global ordering, where qubits are ordered over the whole netlist, and the other based on local ordering for minimizing SWAP gate insertions on smaller segments of netlists. Further reductions in cost are possible by using multi-valued qudits that have more than two basis states. The present paper considers a quantum circuit based on the NCV library, and proposes a better SWAP gate insertion method based on local ordering that uses an N-gate lookahead approach to reduce cost. Experimental results on benchmark circuits and comparison against published works confirm the benefits of the proposed approach, with improvements over reported works obtained in the range of 27%-43% on the average and 54%-63% in the best case. The method is also scalable for larger circuits, with the longest runtime observed as 10 minutes.
2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)
Realization of logic functions using ternary reversible logic is known to requirelesser number of... more Realization of logic functions using ternary reversible logic is known to requirelesser number of lines as compared to conventionalbinary reversible logic. This aspect of ternary reversible logic has motivated researchers to explore various synthesis approaches in the past. Existing synthesis methods require additional lines (called ancilla lines)for synthesis, which is expensive from the quantum implementation pointof view. There is no reported work for ternary reversible logic synthesisthat require the minimum possible number of gates and also lines. Thisclass of synthesis methods is called exact synthesis. In this paper two exact synthesis methods for ternary reversible logic have been proposed for the first time, one based on booleansatisfiability (SAT) and the other based on level-constrained heuristic search technique. A permutation representing a reversible ternary truth table is given as input, and a reversible circuit consisting ofgeneralized ternary Toffoli gates that implements the permutationis obtained as output. Experimental studies have been carried out on various randomly generatedternary reversible functions.