Adam Postula - Academia.edu (original) (raw)

Papers by Adam Postula

Research paper thumbnail of Wireless Position Location System for Indoor Environments

Location systems are used for a variety of navigation applications. Current Location systems are ... more Location systems are used for a variety of navigation applications. Current Location systems are designed to provide accurate distance position coordinates. There are tracking or logistic applications where actual position coordinates are not necessary. Determining the room in a building an object is located can be more useful then the actual coordinates. We present an inexpensive and robust wireless location beacon network that can track the location of emergency responders or users in an indoor environment. Location beacons are placed at predetermined positions in a building. The location beacons are used to determine the presence of the user in an area of a building. The location beacon network does not track the user's coordinates. The location beacon network uses the ZigBee/802.15.4 wireless communications protocol. Our paper examines the use of the Zigbee protocol to determine a user’s location. Two realtime location tracking mechanisms are also analysed and tested. A succ...

Research paper thumbnail of A comparison of interval methods in symbolic circuit analysis applications

Research paper thumbnail of A bluetooth wireless network infrastructure for multimedia guidebooks on mobile computing devices

Research paper thumbnail of FPGA-accelerated simulation engine for non-viral gene delivery

2015 9th International Conference on Signal Processing and Communication Systems (ICSPCS), 2015

Computational methods have become an important part of gene delivery research, as they allow rese... more Computational methods have become an important part of gene delivery research, as they allow researchers to experiment with different models of cellular processes. Models of the gene delivery process based on telecommunication theory make this experimentation especially efficient. Therefore, this paper presents a specialised FPGA-accelerated heterogeneous architecture for simulating the gene delivery process using queuing theory. We also present an implementation of a programmable M/M/∞ queue simulator, and compare its performance to that of an equivalent software simulator. We finally discuss limitations of our system and outline future work aimed at further performance improvement.

Research paper thumbnail of Cities: Performing Combinatorial Optimisation Using Linked Lists On Special Purpose Computers

This paper addresses the development of general purpose meta-heuristic based combinatorial optimi... more This paper addresses the development of general purpose meta-heuristic based combinatorial optimisation algorithms. With this system, a user can specify a problem in a high level algebraic language based on linked list data structures, rather than conventional vector notation. The new formulation is much more concise than the vector form, and lends itself to search heuristics based on local neighbourhood operators . The specification is then compiled into C code, and a unique solver is generated for each particular problem. Currently, search engines for simulated annealing, greedy search and Tabu search have been implemented, and good results have been achieved over a wide range of optimisation problems. We have also implemented a special purpose computer that solves one particular optimisation problem formulated using this technique, namely the travelling salesman problem. Solvers have been produced for simulated annealing, greedy and Tabu search, and a speedup up to 16 times has been achieved over a high-end workstation. 1 Introduction

Research paper thumbnail of Wireless interactive system for patient healthcare monitoring using mobile computing devices

2008 2nd International Conference on Signal Processing and Communication Systems, 2008

Research paper thumbnail of GBLD: A Formal Model for Layout Description and Generation

In this paper, we introduce a layout description and generation model, GBLD, based on the notions... more In this paper, we introduce a layout description and generation model, GBLD, based on the notions and elements of L-systems and context-free grammars. Our layout model is compatible with geometric layout formats, such as GDSII or CIF. However, it is more powerful and more concise. The layouts represented by GBLD are sizeable, parameterised, and can incorporate design rules. GBLD has the potential to be used as a format for analog layout templates, analog layout retargeting, as well as the final layout format.

Research paper thumbnail of Location based services with personal area network for community and tourism applications

The Infopoint Explorer is an outdoor wireless personal area network for location-based services t... more The Infopoint Explorer is an outdoor wireless personal area network for location-based services that allows users to access locality information interactively using mobile computing devices such as PDAs and smartphones. The Infopoint explorer was used to study the limitations imposed by inexpensive and popular wireless technologies such as Bluetooth for outdoor location-based services. The Infopoint Explorer functioned as a multimedia guidebook that allowed access to location-specific information using wireless Infopoints. The Infopoints detect and attempt to transfer multimedia content to nearby mobile computing devices using Bluetooth connectivity. An adaptive Bluetooth Inquiry Access Code algorithm was developed to reduce the time taken for the Infopoint to detect nearby devices. The Infopoint was deployed for a four-month trial.

Research paper thumbnail of A Tail of 2N cities: Performing Combinatorial Optimisation using Linked Lists on Special Purpose Computers

This paper addresses the development of general purpose meta-heuristic based combinatorial optimi... more This paper addresses the development of general purpose meta-heuristic based combinatorial optimisation algorithms. With this system, a user can specify a problem in a high level algebraic language based on linked list data structures, rather than conventional vector notation. The new formulation is much more concise than the vector form, and lends itself to search heuristics based on local neighbourhood operators . The specification is then compiled into C code, and a unique solver is generated for each particular problem. Currently, search engines for simulated annealing, greedy search and Tabu search have been implemented, and good results have been achieved over a wide range of optimisation problems.

Research paper thumbnail of Synthesis for Prototyping of Application Specific Processors

ABSTRACT This paper presents our experience with the development of Application Specific Processo... more ABSTRACT This paper presents our experience with the development of Application Specific Processors (ASP) for simulation and optimization problems. The focus is on the design methodology that allows rapid development of application specific processors. As a design case we describe and analyse the design process applied to the development of a specialised processor for simulation of sintering in metallurgical research.

Research paper thumbnail of Symbolic analysis of the Tau Cell log-domain filter using affine MOSFET models

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010

Research paper thumbnail of Interconnect centred design methodology for system-on-a-chip integration

Research paper thumbnail of <title>Efficient simplification strategies for symbolic circuit expressions of linear analog integrated circuits</title>

Microelectronics: Design, Technology, and Packaging II, 2005

ABSTRACT

Research paper thumbnail of Solving synthesis problems with genetic algorithms

Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204)

ABSTRACT

Research paper thumbnail of Test strategies on functionally partitioned module-based programmable architecture for base-band processing

Proceedings Euromicro Symposium on Digital Systems Design, 2001

A specialised recon$gurable architecture for telecommunication base-band processing is augmented ... more A specialised recon$gurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing ...

Research paper thumbnail of Self-Organising Maps in Computer Aided Design of electronic circuits

Kohonen Maps, 1999

Publisher Summary Computer Aided Design (CAD) of electronic circuits is very dependent on effecti... more Publisher Summary Computer Aided Design (CAD) of electronic circuits is very dependent on effective optimization algorithms. Several neural network paradigms have been explored in application to optimization problems in CAD and Kohonen's self-organizing maps (SOM) have proved to be one of the most successful. It focuses on mapping to SOM scheduling, and binding the processes that are crucial for optimizations in high level synthesis (HLS). Research on hardware synthesis provides methodology and optimization algorithms for automation of the design process. As the design problems span from placement of transistors to simulation or testing of a whole system, a large variety of different optimization algorithms can be found in research literature. Among those investigated lately are approaches based on neural networks and self organization maps apply to lower level hardware design problems. As the need for higher level tools increases rapidly, it is of much interest to explore the possibilities created by those new approaches in this area. The SOM based algorithms have been implemented and have formed the optimization kernel of the synthesis system SYNT that was later developed into a commercial tool.

Research paper thumbnail of Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis

This paper presents a new layout parasitic extraction paradigm, symbolic extraction, for use in l... more This paper presents a new layout parasitic extraction paradigm, symbolic extraction, for use in layout-aware analog synthesis methodologies. Unlike traditional post-layout extraction, symbolic extraction extracts layout parasitics in symbolic form from parameterized layouts. As a result, parasitic values can be calculated directly from given circuit and layout parameters. In layout-aware circuit synthesis process, tasks of time-consuming layout re-generation and re- extraction can be replaced by this fast parasitics calculation step. In the paper, we discuss how to integrate symbolic extraction into the existing analog design flow and how symbolic extraction can be implemented.

Research paper thumbnail of A divide and conquer approach for System Level Verification of DSP ASICs

Proc. IEEE Int. High …, 1999

Abstract. Verification of modern DSP ASICs has become a very complex problem since many DSP block... more Abstract. Verification of modern DSP ASICs has become a very complex problem since many DSP blocks placed on a chip require a complicated global control logic for their proper interaction. Verifying DSP blocks together with the global control results in combinatorial ...

Research paper thumbnail of The virtual prototyping of an AM chip using grammar based approach

the Proc. of the 17th IEEE …, 1999

Page 1. The Virtual Prototyping of an AM Chip Using Grammar %ased Approach Abhijit K. Deb,Ahmed H... more Page 1. The Virtual Prototyping of an AM Chip Using Grammar %ased Approach Abhijit K. Deb,Ahmed Hemani, Adam Postula ESD Lab, Royal Institute of Technology, Electrum-229, S-164 40 Kista, Sweden abhijit | ahmed | adam @ ele.kth.se Ladimer S. Nagurney Dept. ...

Research paper thumbnail of Using RFID and bluetooth for localised interaction with wireless embedded internet devices

Research paper thumbnail of Wireless Position Location System for Indoor Environments

Location systems are used for a variety of navigation applications. Current Location systems are ... more Location systems are used for a variety of navigation applications. Current Location systems are designed to provide accurate distance position coordinates. There are tracking or logistic applications where actual position coordinates are not necessary. Determining the room in a building an object is located can be more useful then the actual coordinates. We present an inexpensive and robust wireless location beacon network that can track the location of emergency responders or users in an indoor environment. Location beacons are placed at predetermined positions in a building. The location beacons are used to determine the presence of the user in an area of a building. The location beacon network does not track the user's coordinates. The location beacon network uses the ZigBee/802.15.4 wireless communications protocol. Our paper examines the use of the Zigbee protocol to determine a user’s location. Two realtime location tracking mechanisms are also analysed and tested. A succ...

Research paper thumbnail of A comparison of interval methods in symbolic circuit analysis applications

Research paper thumbnail of A bluetooth wireless network infrastructure for multimedia guidebooks on mobile computing devices

Research paper thumbnail of FPGA-accelerated simulation engine for non-viral gene delivery

2015 9th International Conference on Signal Processing and Communication Systems (ICSPCS), 2015

Computational methods have become an important part of gene delivery research, as they allow rese... more Computational methods have become an important part of gene delivery research, as they allow researchers to experiment with different models of cellular processes. Models of the gene delivery process based on telecommunication theory make this experimentation especially efficient. Therefore, this paper presents a specialised FPGA-accelerated heterogeneous architecture for simulating the gene delivery process using queuing theory. We also present an implementation of a programmable M/M/∞ queue simulator, and compare its performance to that of an equivalent software simulator. We finally discuss limitations of our system and outline future work aimed at further performance improvement.

Research paper thumbnail of Cities: Performing Combinatorial Optimisation Using Linked Lists On Special Purpose Computers

This paper addresses the development of general purpose meta-heuristic based combinatorial optimi... more This paper addresses the development of general purpose meta-heuristic based combinatorial optimisation algorithms. With this system, a user can specify a problem in a high level algebraic language based on linked list data structures, rather than conventional vector notation. The new formulation is much more concise than the vector form, and lends itself to search heuristics based on local neighbourhood operators . The specification is then compiled into C code, and a unique solver is generated for each particular problem. Currently, search engines for simulated annealing, greedy search and Tabu search have been implemented, and good results have been achieved over a wide range of optimisation problems. We have also implemented a special purpose computer that solves one particular optimisation problem formulated using this technique, namely the travelling salesman problem. Solvers have been produced for simulated annealing, greedy and Tabu search, and a speedup up to 16 times has been achieved over a high-end workstation. 1 Introduction

Research paper thumbnail of Wireless interactive system for patient healthcare monitoring using mobile computing devices

2008 2nd International Conference on Signal Processing and Communication Systems, 2008

Research paper thumbnail of GBLD: A Formal Model for Layout Description and Generation

In this paper, we introduce a layout description and generation model, GBLD, based on the notions... more In this paper, we introduce a layout description and generation model, GBLD, based on the notions and elements of L-systems and context-free grammars. Our layout model is compatible with geometric layout formats, such as GDSII or CIF. However, it is more powerful and more concise. The layouts represented by GBLD are sizeable, parameterised, and can incorporate design rules. GBLD has the potential to be used as a format for analog layout templates, analog layout retargeting, as well as the final layout format.

Research paper thumbnail of Location based services with personal area network for community and tourism applications

The Infopoint Explorer is an outdoor wireless personal area network for location-based services t... more The Infopoint Explorer is an outdoor wireless personal area network for location-based services that allows users to access locality information interactively using mobile computing devices such as PDAs and smartphones. The Infopoint explorer was used to study the limitations imposed by inexpensive and popular wireless technologies such as Bluetooth for outdoor location-based services. The Infopoint Explorer functioned as a multimedia guidebook that allowed access to location-specific information using wireless Infopoints. The Infopoints detect and attempt to transfer multimedia content to nearby mobile computing devices using Bluetooth connectivity. An adaptive Bluetooth Inquiry Access Code algorithm was developed to reduce the time taken for the Infopoint to detect nearby devices. The Infopoint was deployed for a four-month trial.

Research paper thumbnail of A Tail of 2N cities: Performing Combinatorial Optimisation using Linked Lists on Special Purpose Computers

This paper addresses the development of general purpose meta-heuristic based combinatorial optimi... more This paper addresses the development of general purpose meta-heuristic based combinatorial optimisation algorithms. With this system, a user can specify a problem in a high level algebraic language based on linked list data structures, rather than conventional vector notation. The new formulation is much more concise than the vector form, and lends itself to search heuristics based on local neighbourhood operators . The specification is then compiled into C code, and a unique solver is generated for each particular problem. Currently, search engines for simulated annealing, greedy search and Tabu search have been implemented, and good results have been achieved over a wide range of optimisation problems.

Research paper thumbnail of Synthesis for Prototyping of Application Specific Processors

ABSTRACT This paper presents our experience with the development of Application Specific Processo... more ABSTRACT This paper presents our experience with the development of Application Specific Processors (ASP) for simulation and optimization problems. The focus is on the design methodology that allows rapid development of application specific processors. As a design case we describe and analyse the design process applied to the development of a specialised processor for simulation of sintering in metallurgical research.

Research paper thumbnail of Symbolic analysis of the Tau Cell log-domain filter using affine MOSFET models

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010

Research paper thumbnail of Interconnect centred design methodology for system-on-a-chip integration

Research paper thumbnail of <title>Efficient simplification strategies for symbolic circuit expressions of linear analog integrated circuits</title>

Microelectronics: Design, Technology, and Packaging II, 2005

ABSTRACT

Research paper thumbnail of Solving synthesis problems with genetic algorithms

Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204)

ABSTRACT

Research paper thumbnail of Test strategies on functionally partitioned module-based programmable architecture for base-band processing

Proceedings Euromicro Symposium on Digital Systems Design, 2001

A specialised recon$gurable architecture for telecommunication base-band processing is augmented ... more A specialised recon$gurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing ...

Research paper thumbnail of Self-Organising Maps in Computer Aided Design of electronic circuits

Kohonen Maps, 1999

Publisher Summary Computer Aided Design (CAD) of electronic circuits is very dependent on effecti... more Publisher Summary Computer Aided Design (CAD) of electronic circuits is very dependent on effective optimization algorithms. Several neural network paradigms have been explored in application to optimization problems in CAD and Kohonen's self-organizing maps (SOM) have proved to be one of the most successful. It focuses on mapping to SOM scheduling, and binding the processes that are crucial for optimizations in high level synthesis (HLS). Research on hardware synthesis provides methodology and optimization algorithms for automation of the design process. As the design problems span from placement of transistors to simulation or testing of a whole system, a large variety of different optimization algorithms can be found in research literature. Among those investigated lately are approaches based on neural networks and self organization maps apply to lower level hardware design problems. As the need for higher level tools increases rapidly, it is of much interest to explore the possibilities created by those new approaches in this area. The SOM based algorithms have been implemented and have formed the optimization kernel of the synthesis system SYNT that was later developed into a commercial tool.

Research paper thumbnail of Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis

This paper presents a new layout parasitic extraction paradigm, symbolic extraction, for use in l... more This paper presents a new layout parasitic extraction paradigm, symbolic extraction, for use in layout-aware analog synthesis methodologies. Unlike traditional post-layout extraction, symbolic extraction extracts layout parasitics in symbolic form from parameterized layouts. As a result, parasitic values can be calculated directly from given circuit and layout parameters. In layout-aware circuit synthesis process, tasks of time-consuming layout re-generation and re- extraction can be replaced by this fast parasitics calculation step. In the paper, we discuss how to integrate symbolic extraction into the existing analog design flow and how symbolic extraction can be implemented.

Research paper thumbnail of A divide and conquer approach for System Level Verification of DSP ASICs

Proc. IEEE Int. High …, 1999

Abstract. Verification of modern DSP ASICs has become a very complex problem since many DSP block... more Abstract. Verification of modern DSP ASICs has become a very complex problem since many DSP blocks placed on a chip require a complicated global control logic for their proper interaction. Verifying DSP blocks together with the global control results in combinatorial ...

Research paper thumbnail of The virtual prototyping of an AM chip using grammar based approach

the Proc. of the 17th IEEE …, 1999

Page 1. The Virtual Prototyping of an AM Chip Using Grammar %ased Approach Abhijit K. Deb,Ahmed H... more Page 1. The Virtual Prototyping of an AM Chip Using Grammar %ased Approach Abhijit K. Deb,Ahmed Hemani, Adam Postula ESD Lab, Royal Institute of Technology, Electrum-229, S-164 40 Kista, Sweden abhijit | ahmed | adam @ ele.kth.se Ladimer S. Nagurney Dept. ...

Research paper thumbnail of Using RFID and bluetooth for localised interaction with wireless embedded internet devices