Adnan Harb - Academia.edu (original) (raw)

Papers by Adnan Harb

2022 International Conference on Smart Systems and Power Management (IC2SPM)

2017 29th International Conference on Microelectronics (ICM)

This paper addresses the applicability of using DeviceNet — an industrial network — to optimize S... more This paper addresses the applicability of using DeviceNet — an industrial network — to optimize Solar PV Systems. The design permits accurate and reliable monitoring, feedback, and controlling of every PV solar related device to detect the faulted, cracked, or malfunctioning panel. DeviceNet does not only handles I/O monitoring, diagnostics, Panel tracking, etc. but it also can power up certain devices without extra power sources or wires. This system is capable to communicate to several PLCs and HMIs that can be used as advanced SCADAs. This paper, considers a reliable industrial networking — DeviceNet and perspectives to achieve a smart green system for a specific PV area with minimum cost and lowest energy consumption that is self-powered by the solar system itself.

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Journal of Electronic Testing, 2021

AEU - International Journal of Electronics and Communications, 2018

Une interface cmos à basse puissance pour l'enregistrement et le traitement de signaux de trè... more Une interface cmos à basse puissance pour l'enregistrement et le traitement de signaux de très faible amplitude -- Un circuit de redressement et d'intégration par période à capacités commutées pour le traitement des signaux nerveux

2019 31st International Conference on Microelectronics (ICM), 2019

The paper shows a design of mm-wave low noise power amplifier LNPA. The amplifier has the functio... more The paper shows a design of mm-wave low noise power amplifier LNPA. The amplifier has the function of LNA in addition to power amplifier PA. It generates large output power taking into account the low noise figure of the amplifier stage. A variable and controlled power gain of 10 dB is designed in the STM 28-nm FD-SOI technology at the candidate of the 5G frequency 25 GHz. The post layout simulation of a mathbf522x220mumathbfm2\mathbf{522x220}\ \mu \mathbf{m}^{2}mathbf522x220mumathbfm2 layout area shows a 2.8 dB noise figure, 13.7 dBm saturated output power and 34.8% PAE using differential amplifier topology.

2017 29th International Conference on Microelectronics (ICM), 2017

Nowadays, technological demands are exponentially and rapidly growing. The telecommunication mark... more Nowadays, technological demands are exponentially and rapidly growing. The telecommunication market examines a growing demand for RF mobile devices where high latency performances are targeted. The power amplifier is a major element of the radio frequency front-end especially if power consumption and bandwidth are considered. This paper presents the design of mm-wave power amplifier for the candidate of 5G using both Common Source Class-AB and Class-J topologies by means of the 28-nm UTBB FD-SOI technology under body bias technique. Upon taking into consideration the parasitic extraction of the transistor, RF pads, and interconnection to ground, a comparison is made and the theoretical effectiveness of Class-J topology for single stage large signal amplification is simulated practically. Moreover, two distinct transistor widths 250 μm and 350 μm are simulated where each has its own topology to study the impact of increasing the width on the performance of the Power Amplifier. While 5G spectral band is not yet specified and determined; recent studies proved that the 28 GHz band is particularly effective for 5G mobile standardization. Thus, the 28 GHz band is chosen as the fundamental frequency of the operation for this work.

2018 IEEE International Multidisciplinary Conference on Engineering Technology (IMCET)

5G is the next wireless technology that is expected to be launched in 2020. Electromagnetic radia... more 5G is the next wireless technology that is expected to be launched in 2020. Electromagnetic radiations emitted by mobile phones resulted in considerably higher brain tissue exposure than other radiation sources in the radiofrequency band, which led to concerns about the possible potential health effects from exposure to Radio Frequency (RF) and Millimeter (mm) wave radiations. This paper investigates the effects of 5G radiations for different frequency candidates on human brain. This has been achieved by using Computer Simulation Technology (CST) software by conducting simulations on Specific Anthropomorphic Mannequin (SAM); a model designed according to different international standards representing the average material properties of the head by calculating the Specific Absorption Rate (SAR, a quantitative measure of interaction mechanisms of radiofrequency radiation with the living systems and expressed in watt per kilogram (W/kg) in order to check whether the resulting exposure is safe or not by comparing it to the safety limit of exposure to high frequency radiations set by different international standards.

International Conference on Computational Intelligence, 2004

2017 29th International Conference on Microelectronics (ICM)

This paper presents an only hardware description language (HDL)-based serial link (SerDes) design... more This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10−12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s.

2018 International Conference on Computer and Applications (ICCA)

In this paper, we present the design of a multiplier, an activation function and its derivative b... more In this paper, we present the design of a multiplier, an activation function and its derivative blocks to realize a neural network based on the Multi-Layer Perceptron with back propagation (MLP) algorithm. The network and the building blocks are validated using Simulink simulations. This is to help in the future to build the equivalent blocks in Analog CMOS circuits.

2017 29th International Conference on Microelectronics (ICM), 2017

This paper presents the design of a programmable signal generator to produce the inputs and the d... more This paper presents the design of a programmable signal generator to produce the inputs and the desired outputs to test an integrated circuit IC dedicated for neural network application (on chip learning). The main blocks for this design are a microcontroller PIC18F2680, a multiplexer 4067, and an LCD LM032L. The outputs of the programmable signal generator have an amplitude up to 1 V at a frequency up to 5 KHz, which is sufficient for our application, i.e. the breast cancer detection.

Static Random-Access Memories (SRAMs) are an integral part of the chip industry, occupying a noti... more Static Random-Access Memories (SRAMs) are an integral part of the chip industry, occupying a noticeable share of the memory market due to their high performance and compatibility with CMOS technology. Traditional SRAMs lack the capability to retain data after power-off, restricting their availability in applications such as battery-powered mobile devices where non-volatility associated with zero-leakage currents is needed. This paper presents a novel Non-Volatile SRAMs (NVSRAMs) device based on Resistive RAM (RRAM) technology. A comparison between SRAM and NVSRAM performances is proposed at both cell and memory array level. The comparison covers several metrics such as power consumption, area and design complexity. The presented circuits are implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.

This paper presents a second-order distortion improvement technique based on the mitigation of ra... more This paper presents a second-order distortion improvement technique based on the mitigation of radiated local-oscillator (LO) to radio-frequency (RF) leakage. This leakage might become one of the major sources for IIP2 degradation due to massive floorplanning and placement proximity constraints between high-power and sensitive RF blocks in modern multiband and large-scale integrated radio receivers. IIP2 performance is also constrained by low power requirements in multiple-interference wireless applications such as the internet-of-things (IoT) and wireless sensor networks. The proposed technique employs 8-shaped coils in both down-converter mixer and LO generation circuits while presenting an area-effective solution with normal coils being directly replaced by 8-shaped coils within the same area. The presented solution involves zero extra power consumption and negligible noise degradation due to slight decrease in the coils quality-factor. The relative advantages have been demonstra...

2016 Third International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA), 2016

This paper presents a start-up boost technique dedicated to BiCMOS LC-oscillators. The proposed t... more This paper presents a start-up boost technique dedicated to BiCMOS LC-oscillators. The proposed technique is applied to wide-band LC-VCOs which generally suffer from increased tank losses and require high bias current to ensure start-up and sustainable oscillation. To overcome these limitations, we propose to connect a bipolar transconductance to intermediate levels of the oscillator's tank in order to enhance the global transconductance and boost the start-up while relaxing the total power consumption. The constraints of the auxiliary transconductance use as well as the achieved improvements relative to power saving are discussed in this paper. In addition, an LC-VCO design using the proposed technique in 0.25-μm BiCMOS technology is described. The oscillator covers the frequency range from 4.82 GHz to 9.86 GHz with 68.7% tuningrange. The achieved phase noise at 1-MHz offset varies from -121 dBc/Hz to -116 dBc/Hz, at 5.24 GHz and 8.8 GHz, respectively, with a maximum power consumption of 18.6 mW from 1.2-V DC supply voltage.

Journal of Education and Practice, 2014

2013 25th International Conference on Microelectronics (ICM), 2013

ABSTRACT The paper presents the design of MEMS-based sensory system for real-time bacteria detect... more ABSTRACT The paper presents the design of MEMS-based sensory system for real-time bacteria detection. The principle of functioning is based on monitoring the variation in capacitance signals owing to the adherence of target bacteria to the sensing interface. The system is designed using custom-based technology and it consists of comb finger capacitor structures made out of doped polysilicon. Aiming at improving the detection efficiency, the space between the comb fingers, forming the two electrodes of the capacitive sensor, will be made porous through a post-processing with Xenon Difluoride (XeF2) dry etching technique. This allows entrapping bacteria in between the electrodes thus increasing the variation of capacitance. This latter, is acquired using a Charge Based Capacitance Measurement (CBCM) sensory circuit built with to the 0.13 μm CMOS technology. The circuit is able to detect a difference in capacitance as low as 0.75 fF.