Adrian Chasin - Academia.edu (original) (raw)

Papers by Adrian Chasin

Ieee Transactions on Electron Devices, 2014

International Journal of Control, 2009

This article presents a new approach for or robust model reduction for uncertain systems based on... more This article presents a new approach for or robust model reduction for uncertain systems based on an optimisation algorithm applied directly in the space of reduced-order model parameters. The proposed approach can be applied to both polytopic or affine parameter-dependent models as well as for continuous or discrete-time systems.The developed procedure is capable of computing both fixed reduced-order model as

IEEE Transactions on Electron Devices, 2013

We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequenc... more We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequency of 1.8 GHz at 0 V bias. These diodes have a rectification ratio of up to 108 at ±1 V and a current density of 800 A/cm2 at +1 V. The diodes' high performance is achieved by understanding and modeling of the two contacts, a Schottky contact using Pd at the bottom and an ohmic contact formed at the top. In particular, the choice of the latter top contact combined with an optimized IGZO layer thickness proves to be crucial: we show how the semiconductor layer thickness and the nature of the top metal modify the doping concentration profile of the IGZO film, which we fully measure and characterize, and how that affects the performance and optimization of the diodes. We measure our diodes in rectifiers, which operate up to 1.1 GHz. Finally, we show that these rectifiers can be fully modeled in SPICE using diode parameters extracted from electrical measurements.

IEEE Electron Device Letters, 2014

We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible... more We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are connected serially, similar to the NAND architecture of flash memory, which offers the highest memory density of transistor memories. We demonstrate a reliable addressing scheme in this architecture, without the need for select or access transistors. As proof of principle, a 1 × 4 NAND-like string is fabricated and characterized. Retention up to one month and endurance up to 2500 cycles are shown. Read and write disturb measurements show that the memory array can potentially be scaled up to 8 kbits.

IEEE Electron Device Letters, 2014

ABSTRACT We present amorphous indium–gallium-zinc oxide Schottky diodes with unprecedented curren... more ABSTRACT We present amorphous indium–gallium-zinc oxide Schottky diodes with unprecedented current densities of 10410^{4}104 and 105rmA˜/rmcm210^{5}~{rm A}/{rm cm}^{2}105rmA˜/rmcm2 at forward biases of 1.5 and 5 V, respectively. The diode presents a high rectification ratio of 101010^{10}1010 at pmrm2rmV˜{pm}{rm 2}~{rm V}pmrm2rmV˜ , which is essential for suppressing the sneak current of not-selected cells in the memory array. In addition, we show that the diode complies with the demanding performance of memory applications. The device degradation, given by a 30% reduction of its forward current after 104rms˜10^{4}~{rm s}104rms˜ of continuous bias stress or 10910^{9}109 pulses cycles, was studied via I−VI{-}VI−V and C−VC{-}VC−V measurements and can be attributed to trapping of electrons at deep acceptor levels, which increases the diode built-in potential. Finally, we show that the device is stable upon thermal stress at 300 circrmC^{circ}{rm C}circrmC for 1 h, which opens the possibility of further processing and integration with the memory cell.

Advanced Materials Interfaces

Advanced Functional Materials

2017 IEEE International Electron Devices Meeting (IEDM)

We assess the degradation of stacked Silicon Gate-All-Around (GAA) Nanowire (NW) nFETs in the ful... more We assess the degradation of stacked Silicon Gate-All-Around (GAA) Nanowire (NW) nFETs in the full {Vg, Vd} bias space. We perform extensive characterization to separate the intrinsic (i.e. the various degradation modes) from extrinsic effects (i.e., parasitic FETs and source/drain series resistance). The modelling of the degradation includes various channel hot-carrier (CHC) modes as well as PBTI and allows an extrapolation to 10-years lifetime in the full bias space. Moreover, by extraction of the activation energies of each of the degradation modes, and by obtaining the thermal resistance by S-parameter measurements, we compensate for any self-heating-induced acceleration or deceleration during overstress. As a result, we obtain a fully intrinsic nGAA-NWFET lifetime map in the entire bias space.

Today {OLAE} {RFID} tags are limited in performance. The {ORICLA} partners elaborate new {OLAE} c... more Today {OLAE} {RFID} tags are limited in performance. The {ORICLA} partners elaborate new {OLAE} chip technologies, based on hybrid complementary logic using p-type organic and n-type solution processed oxide semiconductors. This unique combination leads to demonstration of {OLAE} chips and tags with performance, getting close to requirements for {EPC} item level tagging. The month 18 {ORICLA} demonstrations comprise the integration of the hybrid {CMOS} process on foil {[Rockele} et al., Organic Electronics 12,1909 (2011)] and bidirectional communication (i.e. the tag can understand and talk to the reader) with uplink data rates up to 3.5 kbits/s and downlink data rates up to 21 kbits/s {[Myny} et al, {ISSCC} 2012]. These results have been demonstrated using solution processed oxides at temperatures as low as {250C.} Current work focuses in implementing these hybrid {CMOS} circuits using the new solution processed oxides developed by {EVONIK} that can go down to temperatures as low as {150C.} These low process temperatures will enable to realize the {RFID} tag on low-cost {PEN} foil. A second remaining focus of the {ORICLA} project is to increase the maximum frequency of the oxide rectifiers up to {UHF} frequencies. These frequencies allow reducing the cost of the printed antennas, which enables the path to low-cost {RFID} tags for item level tagging.

2018 IEEE International Reliability Physics Symposium (IRPS)

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms... more Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019

We present a stochastic description of hot-carrier degradation (HCD) which captures the impact of... more We present a stochastic description of hot-carrier degradation (HCD) which captures the impact of random traps (RTs) and random dopants (RDs) using our deterministic physical model for HCD. For each combination of stress voltages and stress time we generate 10,000 different samples with each of them having a unique configuration of RTs and RDs. Our analysis shows that both RTs and RDs broaden the set of degradation traces and device lifetimes, herewith resulting in average (over the sample ensemble) changes in the linear drain current lower than the nominal values from the deterministic model. Although at higher stress voltages device lifetimes follow bimodal normal distributions, at stress biases close to the operating regime the distributions are substantially different. Therefore, a proper modeling of HCD should be based on a full statistical description.

We have demonstrated a metal high-k gate stack with DIT as low as 5.4×1011 cm-2eV-1 at an EOT of ... more We have demonstrated a metal high-k gate stack with DIT as low as 5.4×1011 cm-2eV-1 at an EOT of 10.9 A on a planar Si0.7Ge0.3 MOS capacitor test vehicle without using a Si-cap. The key enablers of the DIT reduction are GeO scavenging process converting GeO into SiO and gate stack nitridation processes. Although the final DIT was found to be highly sensitive to the metal gate deposition process, nitridation of HfO2 was found to negate the negative impact from ALD-based TiN/W. Additional MOS capacitor experiments suggested that the role of the nitridation of HfO2 is to reduce the oxygen diffusivity, resulting in suppressing the undesired oxygen diffusion from the ALD-based metal electrode through the high-k, and resultant interface layer regrowth with additional GeO formation. These results imply that the oxygen profile control throughout the gate stack process is the key to the low-DIT SiGe gate stack.

In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices... more In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {VOV ,VD} stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.

2018 IEEE International Electron Devices Meeting (IEDM)

We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) nnn-/$p$-c... more We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) nnn-/$p$-channel Silicon and strained ppp-channel Germanium Nanowire (NW) transistors. Stress measurements in the entire VG,VD\{V_{G},\ V_{D}\}VG,VD space allow to separate the different degradation modes and how they interact with each other. We show that these degradation modes are not universal, as they have a different relative weight depending on the considered technology, and that they can show different acceleration mechanisms. Moreover, we also discuss the impact of self-heating effects (SHE) by means of activation energy extraction in the entire VG,VD\{V_{G},\ V_{D}\}VG,VD map.

2021 IEEE International Reliability Physics Symposium (IRPS)

We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HC... more We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential- and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

2018 IEEE International Reliability Physics Symposium (IRPS)

We study hot carrier degradation in Si0.75Ge0.25 p-FinFETs by measuring degradation maps in the e... more We study hot carrier degradation in Si0.75Ge0.25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

ECS Transactions

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively levera... more Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV σ(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.

Ieee Transactions on Electron Devices, 2014

International Journal of Control, 2009

This article presents a new approach for or robust model reduction for uncertain systems based on... more This article presents a new approach for or robust model reduction for uncertain systems based on an optimisation algorithm applied directly in the space of reduced-order model parameters. The proposed approach can be applied to both polytopic or affine parameter-dependent models as well as for continuous or discrete-time systems.The developed procedure is capable of computing both fixed reduced-order model as

IEEE Transactions on Electron Devices, 2013

We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequenc... more We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequency of 1.8 GHz at 0 V bias. These diodes have a rectification ratio of up to 108 at ±1 V and a current density of 800 A/cm2 at +1 V. The diodes' high performance is achieved by understanding and modeling of the two contacts, a Schottky contact using Pd at the bottom and an ohmic contact formed at the top. In particular, the choice of the latter top contact combined with an optimized IGZO layer thickness proves to be crucial: we show how the semiconductor layer thickness and the nature of the top metal modify the doping concentration profile of the IGZO film, which we fully measure and characterize, and how that affects the performance and optimization of the diodes. We measure our diodes in rectifiers, which operate up to 1.1 GHz. Finally, we show that these rectifiers can be fully modeled in SPICE using diode parameters extracted from electrical measurements.

IEEE Electron Device Letters, 2014

We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible... more We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are connected serially, similar to the NAND architecture of flash memory, which offers the highest memory density of transistor memories. We demonstrate a reliable addressing scheme in this architecture, without the need for select or access transistors. As proof of principle, a 1 × 4 NAND-like string is fabricated and characterized. Retention up to one month and endurance up to 2500 cycles are shown. Read and write disturb measurements show that the memory array can potentially be scaled up to 8 kbits.

IEEE Electron Device Letters, 2014

ABSTRACT We present amorphous indium–gallium-zinc oxide Schottky diodes with unprecedented curren... more ABSTRACT We present amorphous indium–gallium-zinc oxide Schottky diodes with unprecedented current densities of 10410^{4}104 and 105rmA˜/rmcm210^{5}~{rm A}/{rm cm}^{2}105rmA˜/rmcm2 at forward biases of 1.5 and 5 V, respectively. The diode presents a high rectification ratio of 101010^{10}1010 at pmrm2rmV˜{pm}{rm 2}~{rm V}pmrm2rmV˜ , which is essential for suppressing the sneak current of not-selected cells in the memory array. In addition, we show that the diode complies with the demanding performance of memory applications. The device degradation, given by a 30% reduction of its forward current after 104rms˜10^{4}~{rm s}104rms˜ of continuous bias stress or 10910^{9}109 pulses cycles, was studied via I−VI{-}VI−V and C−VC{-}VC−V measurements and can be attributed to trapping of electrons at deep acceptor levels, which increases the diode built-in potential. Finally, we show that the device is stable upon thermal stress at 300 circrmC^{circ}{rm C}circrmC for 1 h, which opens the possibility of further processing and integration with the memory cell.

Advanced Materials Interfaces

Advanced Functional Materials

2017 IEEE International Electron Devices Meeting (IEDM)

We assess the degradation of stacked Silicon Gate-All-Around (GAA) Nanowire (NW) nFETs in the ful... more We assess the degradation of stacked Silicon Gate-All-Around (GAA) Nanowire (NW) nFETs in the full {Vg, Vd} bias space. We perform extensive characterization to separate the intrinsic (i.e. the various degradation modes) from extrinsic effects (i.e., parasitic FETs and source/drain series resistance). The modelling of the degradation includes various channel hot-carrier (CHC) modes as well as PBTI and allows an extrapolation to 10-years lifetime in the full bias space. Moreover, by extraction of the activation energies of each of the degradation modes, and by obtaining the thermal resistance by S-parameter measurements, we compensate for any self-heating-induced acceleration or deceleration during overstress. As a result, we obtain a fully intrinsic nGAA-NWFET lifetime map in the entire bias space.

Today {OLAE} {RFID} tags are limited in performance. The {ORICLA} partners elaborate new {OLAE} c... more Today {OLAE} {RFID} tags are limited in performance. The {ORICLA} partners elaborate new {OLAE} chip technologies, based on hybrid complementary logic using p-type organic and n-type solution processed oxide semiconductors. This unique combination leads to demonstration of {OLAE} chips and tags with performance, getting close to requirements for {EPC} item level tagging. The month 18 {ORICLA} demonstrations comprise the integration of the hybrid {CMOS} process on foil {[Rockele} et al., Organic Electronics 12,1909 (2011)] and bidirectional communication (i.e. the tag can understand and talk to the reader) with uplink data rates up to 3.5 kbits/s and downlink data rates up to 21 kbits/s {[Myny} et al, {ISSCC} 2012]. These results have been demonstrated using solution processed oxides at temperatures as low as {250C.} Current work focuses in implementing these hybrid {CMOS} circuits using the new solution processed oxides developed by {EVONIK} that can go down to temperatures as low as {150C.} These low process temperatures will enable to realize the {RFID} tag on low-cost {PEN} foil. A second remaining focus of the {ORICLA} project is to increase the maximum frequency of the oxide rectifiers up to {UHF} frequencies. These frequencies allow reducing the cost of the printed antennas, which enables the path to low-cost {RFID} tags for item level tagging.

2018 IEEE International Reliability Physics Symposium (IRPS)

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms... more Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019

We present a stochastic description of hot-carrier degradation (HCD) which captures the impact of... more We present a stochastic description of hot-carrier degradation (HCD) which captures the impact of random traps (RTs) and random dopants (RDs) using our deterministic physical model for HCD. For each combination of stress voltages and stress time we generate 10,000 different samples with each of them having a unique configuration of RTs and RDs. Our analysis shows that both RTs and RDs broaden the set of degradation traces and device lifetimes, herewith resulting in average (over the sample ensemble) changes in the linear drain current lower than the nominal values from the deterministic model. Although at higher stress voltages device lifetimes follow bimodal normal distributions, at stress biases close to the operating regime the distributions are substantially different. Therefore, a proper modeling of HCD should be based on a full statistical description.

We have demonstrated a metal high-k gate stack with DIT as low as 5.4×1011 cm-2eV-1 at an EOT of ... more We have demonstrated a metal high-k gate stack with DIT as low as 5.4×1011 cm-2eV-1 at an EOT of 10.9 A on a planar Si0.7Ge0.3 MOS capacitor test vehicle without using a Si-cap. The key enablers of the DIT reduction are GeO scavenging process converting GeO into SiO and gate stack nitridation processes. Although the final DIT was found to be highly sensitive to the metal gate deposition process, nitridation of HfO2 was found to negate the negative impact from ALD-based TiN/W. Additional MOS capacitor experiments suggested that the role of the nitridation of HfO2 is to reduce the oxygen diffusivity, resulting in suppressing the undesired oxygen diffusion from the ALD-based metal electrode through the high-k, and resultant interface layer regrowth with additional GeO formation. These results imply that the oxygen profile control throughout the gate stack process is the key to the low-DIT SiGe gate stack.

In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices... more In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {VOV ,VD} stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.

2018 IEEE International Electron Devices Meeting (IEDM)

We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) nnn-/$p$-c... more We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) nnn-/$p$-channel Silicon and strained ppp-channel Germanium Nanowire (NW) transistors. Stress measurements in the entire VG,VD\{V_{G},\ V_{D}\}VG,VD space allow to separate the different degradation modes and how they interact with each other. We show that these degradation modes are not universal, as they have a different relative weight depending on the considered technology, and that they can show different acceleration mechanisms. Moreover, we also discuss the impact of self-heating effects (SHE) by means of activation energy extraction in the entire VG,VD\{V_{G},\ V_{D}\}VG,VD map.

2021 IEEE International Reliability Physics Symposium (IRPS)

We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HC... more We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential- and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

2018 IEEE International Reliability Physics Symposium (IRPS)

We study hot carrier degradation in Si0.75Ge0.25 p-FinFETs by measuring degradation maps in the e... more We study hot carrier degradation in Si0.75Ge0.25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

ECS Transactions

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively levera... more Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV σ(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.