Akriti Sinha - Academia.edu (original) (raw)
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This paper presents enhancement in the speed performance of Conventional Wallace tree multiplier ... more This paper presents enhancement in the speed performance of Conventional Wallace tree multiplier by reducing the partial products. Wallace tree multiplier is fabricated using 90nm CMOS technology. In this particular work, we have used 3:2 compressor, 4:2 compressor, 5:2 compressor and carry propagate adder (CPA) to reduce the partial products of conventional Wallace tree multiplier and in compressors we have used 3T EX-OR gates and multiplexers, which eventually results in low cost, low power, high speed multipliers. In this work, we optimised delay, power and area by 90.93%, 75.08%, 84.26% respectively, as compared to conventional one.
This paper presents enhancement in the speed performance of Conventional Wallace tree multiplier ... more This paper presents enhancement in the speed performance of Conventional Wallace tree multiplier by reducing the partial products. Wallace tree multiplier is fabricated using 90nm CMOS technology. In this particular work, we have used 3:2 compressor, 4:2 compressor, 5:2 compressor and carry propagate adder (CPA) to reduce the partial products of conventional Wallace tree multiplier and in compressors we have used 3T EX-OR gates and multiplexers, which eventually results in low cost, low power, high speed multipliers. In this work, we optimised delay, power and area by 90.93%, 75.08%, 84.26% respectively, as compared to conventional one.