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Papers by Alberto Del Barrio

Research paper thumbnail of Power optimization in heterogenous datapaths

Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their wi... more Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we

Research paper thumbnail of Subword Switching Activity Minimization to Optimize Dynamic Power Consumption

IEEE Design & Test of Computers, 2009

This article presents an original high-level synthesis approach that addresses the problem of dyn... more This article presents an original high-level synthesis approach that addresses the problem of dynamic power consumption in data-dominated applications. The proposed scheduling and binding algorithms deal with the switching-activity information, at the variable subword level, to reduce the number of commutations.

Research paper thumbnail of Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis

A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, res... more A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, resource allocation and binding of behavioral specifications. It overcomes the limitations of low-power algorithms and based on a bit-level timing model and a study of the target technology, tries to chain in the same cycle as many operations as possible. It also fragments the functional units, not the operations, for diminishing the required hardware. We also keep a minimum performance by estimating the cycle time while we are chaining operations. This way we obtain a reduction for both the static power and the dynamic one. We achieve an additional dynamic power reduction by studying the Hamming distance and applying partial or total commutative property. Experimental results on real circuits show great improvements in both power and energy consumption and performance over conventional low power algorithms.

Research paper thumbnail of A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2011

Speculative functional units (SFUs) are arithmetic functional units that operate using a predicto... more Speculative functional units (SFUs) are arithmetic functional units that operate using a predictor for the carry signal. The carry prediction helps to shorten the critical path of the functional unit. The average case performance of these units is determined by the hit rate of the prediction. In case of mispredictions, the SFUs need to be coordinated by the datapath control mechanism to perform corrections and to maintain the datapath in the correct state. Devising a control mechanism for correcting mispredictions without adversely impacting overall performance is the most important challenge. In this paper, we present techniques for designing a datapath controller for seamless deployment of SFUs in high level synthesis. We have developed two techniques based on two main control paradigms: centralized and distributed control. The centralized approach stops the execution of the entire datapath for each misprediction and resumes execution once the correct value of the carry is known. The distributed approach decouples the functional unit suffering from the misprediction from the rest of the datapath. Hence, it allows the remainder of the functional units to carry on execution and be at different scheduling states at different times. We tested datapaths utilizing both linear structures and logarithmic structures for speculative arithmetic functional units. Our results show that it is possible to reduce execution time by as much as 38% (33% on average) for linear structures and by as much as 37.2% (25% on average) for logarithmic structures.

Research paper thumbnail of Applying speculation techniques to implement functional units

This paper justifies the use of estimation and prediction of carries to increase the performance ... more This paper justifies the use of estimation and prediction of carries to increase the performance of functional units built with the replication of full adders while keeping a low area penalization. Adders and multipliers are the most representative modules in this group of functional units. The use of these design techniques allows the implementation of modules with performance improvements ranging from 20% to 50% with only an area overheads around 5%. These functional units are suitable for asynchronous circuits but they could also be introduced in synchronous circuits with speculative techniques. The basic idea consists in estimating the carry out from some parts of the functional units, allowing every part to operate independently and in parallel. These modules are connected to build bigger ones. Results from simulations show that for some applications it is possible to make predictions even more accurate that the bit-based estimation. Predictions have also the advantage they can be introduced in the multipliers design, whether estimators cannot. These predictions are similar to the ones used in the branch prediction in a processor.

Research paper thumbnail of Area Optimization of Combined Integer and Floating Point Circuits in High-Level Synthesis

Many scientific applications rely on floating point arithmetic for the dynamic range of represent... more Many scientific applications rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Unfortunately, until recently, floating point units have not been included in ASICs due to their area requirements. The main problem relies on the small reusability degree of these functional units achieved by existing high-level synthesis tools and algorithms. However,

Research paper thumbnail of Aerodynamics Analysis Acceleration through Reconfigurable Hardware

Page 1. AERODYNAMICS ANALYSIS ACCELERATION THROUGH RECONFIGURABLE HARDWARE E. Andres, M. Molina, ... more Page 1. AERODYNAMICS ANALYSIS ACCELERATION THROUGH RECONFIGURABLE HARDWARE E. Andres, M. Molina, G. Botella, A. del Barrio, J. Mendias Dpto. Arquitectura de Computadores y Automatica Universidad Complutense de Madrid eandresp @fdi.ucm.es ...

Research paper thumbnail of Power optimization in heterogenous datapaths

Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their wi... more Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we

Research paper thumbnail of Subword Switching Activity Minimization to Optimize Dynamic Power Consumption

IEEE Design & Test of Computers, 2009

This article presents an original high-level synthesis approach that addresses the problem of dyn... more This article presents an original high-level synthesis approach that addresses the problem of dynamic power consumption in data-dominated applications. The proposed scheduling and binding algorithms deal with the switching-activity information, at the variable subword level, to reduce the number of commutations.

Research paper thumbnail of Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis

A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, res... more A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, resource allocation and binding of behavioral specifications. It overcomes the limitations of low-power algorithms and based on a bit-level timing model and a study of the target technology, tries to chain in the same cycle as many operations as possible. It also fragments the functional units, not the operations, for diminishing the required hardware. We also keep a minimum performance by estimating the cycle time while we are chaining operations. This way we obtain a reduction for both the static power and the dynamic one. We achieve an additional dynamic power reduction by studying the Hamming distance and applying partial or total commutative property. Experimental results on real circuits show great improvements in both power and energy consumption and performance over conventional low power algorithms.

Research paper thumbnail of A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2011

Speculative functional units (SFUs) are arithmetic functional units that operate using a predicto... more Speculative functional units (SFUs) are arithmetic functional units that operate using a predictor for the carry signal. The carry prediction helps to shorten the critical path of the functional unit. The average case performance of these units is determined by the hit rate of the prediction. In case of mispredictions, the SFUs need to be coordinated by the datapath control mechanism to perform corrections and to maintain the datapath in the correct state. Devising a control mechanism for correcting mispredictions without adversely impacting overall performance is the most important challenge. In this paper, we present techniques for designing a datapath controller for seamless deployment of SFUs in high level synthesis. We have developed two techniques based on two main control paradigms: centralized and distributed control. The centralized approach stops the execution of the entire datapath for each misprediction and resumes execution once the correct value of the carry is known. The distributed approach decouples the functional unit suffering from the misprediction from the rest of the datapath. Hence, it allows the remainder of the functional units to carry on execution and be at different scheduling states at different times. We tested datapaths utilizing both linear structures and logarithmic structures for speculative arithmetic functional units. Our results show that it is possible to reduce execution time by as much as 38% (33% on average) for linear structures and by as much as 37.2% (25% on average) for logarithmic structures.

Research paper thumbnail of Applying speculation techniques to implement functional units

This paper justifies the use of estimation and prediction of carries to increase the performance ... more This paper justifies the use of estimation and prediction of carries to increase the performance of functional units built with the replication of full adders while keeping a low area penalization. Adders and multipliers are the most representative modules in this group of functional units. The use of these design techniques allows the implementation of modules with performance improvements ranging from 20% to 50% with only an area overheads around 5%. These functional units are suitable for asynchronous circuits but they could also be introduced in synchronous circuits with speculative techniques. The basic idea consists in estimating the carry out from some parts of the functional units, allowing every part to operate independently and in parallel. These modules are connected to build bigger ones. Results from simulations show that for some applications it is possible to make predictions even more accurate that the bit-based estimation. Predictions have also the advantage they can be introduced in the multipliers design, whether estimators cannot. These predictions are similar to the ones used in the branch prediction in a processor.

Research paper thumbnail of Area Optimization of Combined Integer and Floating Point Circuits in High-Level Synthesis

Many scientific applications rely on floating point arithmetic for the dynamic range of represent... more Many scientific applications rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Unfortunately, until recently, floating point units have not been included in ASICs due to their area requirements. The main problem relies on the small reusability degree of these functional units achieved by existing high-level synthesis tools and algorithms. However,

Research paper thumbnail of Aerodynamics Analysis Acceleration through Reconfigurable Hardware

Page 1. AERODYNAMICS ANALYSIS ACCELERATION THROUGH RECONFIGURABLE HARDWARE E. Andres, M. Molina, ... more Page 1. AERODYNAMICS ANALYSIS ACCELERATION THROUGH RECONFIGURABLE HARDWARE E. Andres, M. Molina, G. Botella, A. del Barrio, J. Mendias Dpto. Arquitectura de Computadores y Automatica Universidad Complutense de Madrid eandresp @fdi.ucm.es ...