Alessandro Trifiletti - Academia.edu (original) (raw)

Papers by Alessandro Trifiletti

2005 IEEE International Symposium on Circuits and Systems, 2005

ABSTRACT Differential power analysis is widely recognized as an extremely powerful and low-cost t... more ABSTRACT Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows us to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.

2005 IEEE International Symposium on Circuits and Systems, 2005

A CMOS current amplifier which provides single-input to differential-output conversion is propose... more A CMOS current amplifier which provides single-input to differential-output conversion is proposed. The circuit exhibits high CMRR and allows an electrical tuning of the current gain. A simple model of the circuit is presented and design guidelines are provided. Simulations with the model parameters of a 0.35-μm process show good agreement with expected results.

The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxia... more The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxial transmission-line transformers. Soft-ferrites are largely used in VHF/UHF components allowing band enlargement on the low-edge side. Degradation of frequency performance on the high-edge side are produced both by ferrite losses, and by parasitic capacitance due to connection to the thermal and electrical ground in high power applications. Both a circuital model for low-power applications and a scalable e.m. model for high-power applications are presented and discussed.

A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against ... more A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order of magnitude lower than in the non-countermeasured case and the correct key is embedded in the measured noise floor.

Lecture Notes in Electrical Engineering, 2009

ABSTRACT Sensor networks are becoming a reality in different applications. As matter to fact, in ... more ABSTRACT Sensor networks are becoming a reality in different applications. As matter to fact, in mobile equipments and battery–operated instrumentation, the design of low–power systems becomes critical, and the vibrating–string strain gauges generally doesn’t work with low tensions of the commercial wi–fi or zegbee modules. In addition, the reduction of the power–supply voltage also degrades the power of the desired signal, while the noise power remains noticeable. So a special interface is necessary. In this work, we propose a highefficiency method based on the gating of the electromagnetic coil of the vibrating–string at the minimum energy to overcome the mechanical damping. Experimental waveforms for a low–cost interface implementation are also given to demonstrate its validity.

International Topical Meeting on Microwave Photonics, 2011

An integrated tool for the analysis and design of optical analog links is proposed, in order to p... more An integrated tool for the analysis and design of optical analog links is proposed, in order to permit optimization of joint performance of the modulator and of its electrical driver within a microwave circuital CAD. The tool comprises a circuital model of the Mach-Zehnder modulator, and a FEM simulator for modulator design from a given physical and geometrical structure. A

1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286), 1999

A novel topology for the offset-compensation and input-matching network of high gain differential... more A novel topology for the offset-compensation and input-matching network of high gain differential amplifiers, tolerant with respect to parasitic effects of bonding wires, is presented. An IC for an optical receiver featuring this network has been designed, and simulations and measurements show high offset suppression (20 dB) and good input matching (1Γinl<-10 dB) over a wide bandwidth (100 kHz-3 GHz)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514), 2000

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been design... more A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f T Silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2 23 -1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.

2008 International Conference on Signals and Electronic Systems, 2008

Abstract A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipe... more Abstract A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic ...

2006 IEEE International Symposium on Circuits and Systems, 2006

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-... more A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), 1999

Clock disabling for power management has been implemented in some microcontrollers, but the wake-... more Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fullydigital clock generator. The CPU is compatible with the PIC16C57 instruction set and supports softwarecontrolled clocking modes -ranging from 44 MHz up to 124 MHz; on-line self-tuning of the maximum full-speed frequency in case of peak-performance requirements; ultra-fast wake-up even with totally disabled clock generator -namely 8.6 ns.

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011

ABSTRACT In this paper we present a low-power low-voltage class- AB amplifier with rail-to-rail o... more ABSTRACT In this paper we present a low-power low-voltage class- AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain of one and two: as the latter is the basic stage of a Multiplying DAC (MDAC), the proposed amplifier may be used to obtain a low-voltage low-power pipeline Analog-to-Digital Converter (ADC). The design has been validated by simulations using the technology models of the STMicroelectronics 65nm CMOS process. The two-stage amplifier has a gain of 26dB at 0.5V, which increases up to 37dB at 1.0V, and a unity gain frequency of 14MHz when supplied at 0.5V, which increases beyond 1GHz at 1.0V. The two SHAs can work at up to 5MSps with a 0.5V supply and consume less than 2μW, showing a THD of -56dB throughout the Nyquist band. Higher sampling frequencies can be obtained increasing the supply voltage and power consumption.

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT A novel architecture for optical beamforming is presented, and its implementation as an ... more ABSTRACT A novel architecture for optical beamforming is presented, and its implementation as an integrated multi-chip system is discussed. Modeling and design methodology of the key components of the system, i.e. the linearized electro-optic external modulator and the array of tunable true delay lines, is detailed. Measurements on a linearized modulator are presented to demonstrate the feasibility of the proposed design approach.

A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard ... more A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 GbE specifications,dual reference clock frequency and output jitter below 80 mUIpp.The phase tracking loop uses a charge pump with low common mode current to minimize frequency ripple.Power supply is 2.5 and 3.3 V and the total power consumption is below 480 mW.

Journal of Cryptographic Engineering, 2015

ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technolo... more ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic (TEL), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation, which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analysis attacks with a Gaussian model have been then mounted against the circuit. Simulation results show that the proposed countermeasure can help to mitigate the electrical mismatches occurring in submicron technologies, offering a promising perspective for the design of power analysis resistant circuits.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of p... more The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of phase-locked loops, due to its ability to operate also in a frequency discriminator mode. However the delay of the feedback path, needed to eliminate the dead zone problem, limits the speed performance of the circuit and its linear input range, and can lead to average differential

2011 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, 2011

A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the des... more A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the design of a transmitter for optical analog links. The model, extracted for a modulator fabricated at Avanex laboratories, has been used to design a circuit in monolithic CMOS technology that provides broad-band improvement of spurious-free dynamic range.

2006 IEEE International Symposium on Circuits and Systems, 2006

A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptog... more A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capa... more ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capability is presented, which allows the design of broadband very high-linearity and high-power amplifiers. Design equations are presented and used to design a 1-2.4 GHz 60W composite amplifier exploiting push-pull configuration.

2005 IEEE International Symposium on Circuits and Systems, 2005

ABSTRACT Differential power analysis is widely recognized as an extremely powerful and low-cost t... more ABSTRACT Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows us to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.

2005 IEEE International Symposium on Circuits and Systems, 2005

A CMOS current amplifier which provides single-input to differential-output conversion is propose... more A CMOS current amplifier which provides single-input to differential-output conversion is proposed. The circuit exhibits high CMRR and allows an electrical tuning of the current gain. A simple model of the circuit is presented and design guidelines are provided. Simulations with the model parameters of a 0.35-μm process show good agreement with expected results.

The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxia... more The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxial transmission-line transformers. Soft-ferrites are largely used in VHF/UHF components allowing band enlargement on the low-edge side. Degradation of frequency performance on the high-edge side are produced both by ferrite losses, and by parasitic capacitance due to connection to the thermal and electrical ground in high power applications. Both a circuital model for low-power applications and a scalable e.m. model for high-power applications are presented and discussed.

A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against ... more A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order of magnitude lower than in the non-countermeasured case and the correct key is embedded in the measured noise floor.

Lecture Notes in Electrical Engineering, 2009

ABSTRACT Sensor networks are becoming a reality in different applications. As matter to fact, in ... more ABSTRACT Sensor networks are becoming a reality in different applications. As matter to fact, in mobile equipments and battery–operated instrumentation, the design of low–power systems becomes critical, and the vibrating–string strain gauges generally doesn’t work with low tensions of the commercial wi–fi or zegbee modules. In addition, the reduction of the power–supply voltage also degrades the power of the desired signal, while the noise power remains noticeable. So a special interface is necessary. In this work, we propose a highefficiency method based on the gating of the electromagnetic coil of the vibrating–string at the minimum energy to overcome the mechanical damping. Experimental waveforms for a low–cost interface implementation are also given to demonstrate its validity.

International Topical Meeting on Microwave Photonics, 2011

An integrated tool for the analysis and design of optical analog links is proposed, in order to p... more An integrated tool for the analysis and design of optical analog links is proposed, in order to permit optimization of joint performance of the modulator and of its electrical driver within a microwave circuital CAD. The tool comprises a circuital model of the Mach-Zehnder modulator, and a FEM simulator for modulator design from a given physical and geometrical structure. A

1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286), 1999

A novel topology for the offset-compensation and input-matching network of high gain differential... more A novel topology for the offset-compensation and input-matching network of high gain differential amplifiers, tolerant with respect to parasitic effects of bonding wires, is presented. An IC for an optical receiver featuring this network has been designed, and simulations and measurements show high offset suppression (20 dB) and good input matching (1Γinl<-10 dB) over a wide bandwidth (100 kHz-3 GHz)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514), 2000

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been design... more A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f T Silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2 23 -1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.

2008 International Conference on Signals and Electronic Systems, 2008

Abstract A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipe... more Abstract A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic ...

2006 IEEE International Symposium on Circuits and Systems, 2006

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-... more A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), 1999

Clock disabling for power management has been implemented in some microcontrollers, but the wake-... more Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fullydigital clock generator. The CPU is compatible with the PIC16C57 instruction set and supports softwarecontrolled clocking modes -ranging from 44 MHz up to 124 MHz; on-line self-tuning of the maximum full-speed frequency in case of peak-performance requirements; ultra-fast wake-up even with totally disabled clock generator -namely 8.6 ns.

2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011

ABSTRACT In this paper we present a low-power low-voltage class- AB amplifier with rail-to-rail o... more ABSTRACT In this paper we present a low-power low-voltage class- AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain of one and two: as the latter is the basic stage of a Multiplying DAC (MDAC), the proposed amplifier may be used to obtain a low-voltage low-power pipeline Analog-to-Digital Converter (ADC). The design has been validated by simulations using the technology models of the STMicroelectronics 65nm CMOS process. The two-stage amplifier has a gain of 26dB at 0.5V, which increases up to 37dB at 1.0V, and a unity gain frequency of 14MHz when supplied at 0.5V, which increases beyond 1GHz at 1.0V. The two SHAs can work at up to 5MSps with a 0.5V supply and consume less than 2μW, showing a THD of -56dB throughout the Nyquist band. Higher sampling frequencies can be obtained increasing the supply voltage and power consumption.

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT A novel architecture for optical beamforming is presented, and its implementation as an ... more ABSTRACT A novel architecture for optical beamforming is presented, and its implementation as an integrated multi-chip system is discussed. Modeling and design methodology of the key components of the system, i.e. the linearized electro-optic external modulator and the array of tunable true delay lines, is detailed. Measurements on a linearized modulator are presented to demonstrate the feasibility of the proposed design approach.

A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard ... more A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 GbE specifications,dual reference clock frequency and output jitter below 80 mUIpp.The phase tracking loop uses a charge pump with low common mode current to minimize frequency ripple.Power supply is 2.5 and 3.3 V and the total power consumption is below 480 mW.

Journal of Cryptographic Engineering, 2015

ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technolo... more ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic (TEL), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation, which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analysis attacks with a Gaussian model have been then mounted against the circuit. Simulation results show that the proposed countermeasure can help to mitigate the electrical mismatches occurring in submicron technologies, offering a promising perspective for the design of power analysis resistant circuits.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of p... more The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of phase-locked loops, due to its ability to operate also in a frequency discriminator mode. However the delay of the feedback path, needed to eliminate the dead zone problem, limits the speed performance of the circuit and its linear input range, and can lead to average differential

2011 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, 2011

A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the des... more A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the design of a transmitter for optical analog links. The model, extracted for a modulator fabricated at Avanex laboratories, has been used to design a circuit in monolithic CMOS technology that provides broad-band improvement of spurious-free dynamic range.

2006 IEEE International Symposium on Circuits and Systems, 2006

A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptog... more A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capa... more ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capability is presented, which allows the design of broadband very high-linearity and high-power amplifiers. Design equations are presented and used to design a 1-2.4 GHz 60W composite amplifier exploiting push-pull configuration.