Alex Bystrov - Academia.edu (original) (raw)

Papers by Alex Bystrov

Dual-rail code, return-to-spacer protocol and hazard-free logic is used to make power consumption... more Dual-rail code, return-to-spacer protocol and hazard-free logic is used to make power consumption of synchronous circuits independent from data processed. A new compact dual-rail flip-flop is designed, whose power consumption is also data-independent. A method for negative gate optimisation of dual-rail logic is described, which results in faster and smaller circuits. A tool for dual-rail circuit optimisation is developed. The tool is interfaced to the Cadence CAD system. Dual-rail and single-rail benchmarks are simulated and compared.

The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to... more The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometer silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibility to environmental and operation-induced interference are physical constraints that drive the development of low-power, process-tolerant design techniques. However, these techniques generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools. You are invited to participate in LPonTR'10. Papers are invited that address current trends, challenges and proposed solutions in the following areas (but are not limited to): • Power and process variations aware design and test • Challenges of Ultra Low-power design on test and reliability • Design for Variability and its effec...

Eleventh IEEE European Test Symposium (ETS'06)

A new low-cost low-complexity checker for online testing of asynchronous interfaces in globally-a... more A new low-cost low-complexity checker for online testing of asynchronous interfaces in globally-asynchronous locally-synchronous circuits is proposed. The solution is fully based upon the standard gate libraries. The checker itself is fully offline testable. It also provides a fault-locating functionality, which is achieved by combining the online mode with scan techniques.

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), 2007

This article will form part of a virtual special issue of the journal, presenting some highlights... more This article will form part of a virtual special issue of the journal, presenting some highlights of the 12th Biennial Conference on High-Resolution X-ray Diffraction and Imaging (XTOP2014).

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007

A logic design style known as phase difference-based logic (PDBL) has several benefits with respe... more A logic design style known as phase difference-based logic (PDBL) has several benefits with respect to security and testing. An existing design method for PDBL circuits has so far been lacking an important component, a register. In this paper, we present the design of a speed independent PDBL register and a timed PDBL register, which can be used in asynchronous or synchronous circuits. Comparisons are presented in terms of speed, size, and power consumption.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011

A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components ba... more A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Cryptographic circuit specifications are refined and passed to optimization and mapping tools for mapping to a library of power-balanced components. Logic optimization tools are then applied to generate secure synchronous circuits for layout generation. This paper presents a new technique for evaluating the security of such circuits in particular those which offer a higher level of protection. A security metric is introduced which is based on the common selection function that is widely used in DPA attacks and a correlation measure similar to the one used in CPA attacks. This is used to compare the security level for these kinds of balanced circuits that are more difficult to attack. The paper shows that the circuits generated are more efficient and can offer a higher level of security than those generated by alternative techniques. NCL-EECE-MSD-TR-2010-152, University of Newcastle Upon Tyne F. Burns, A. Bystrov, A. Koelmans and A. Yakovlev: Design and security evaluation of balanced 1-of-n circuits out in [7]. This was primarily applied at the lower level using a library of differential balanced cells [8] and was targetted towards power-balanced synchronous circuits. In [9] they investigated side-channel attacks at the lower level and concluded the best solution to power analysis is to embed countermeasures into logic cells [10] to reduce leakage information. Here a novel logic style is proposed which relies on the use of signals with three different possible states operating with a power consumption independent of both the logic values and the sequence of data. An alternative technique uses dual-rail [11] where the logic of dual-rail provides the security because of the 1-of-2 encoding used. Dual-rail provides in addition to security against side-channel attacks [12] a level of protection at the fault-level [13] as well. Unfortunately it suffers from significant overheads in area and power. A demonstrator chip based on an alternating spacer protocol attempts to overcome this problem by utilizing a low-overhead dual-rail logic style [14]. Attempts at using dual-rail for asynchronous solutions has so far proved to be useful but unfortunately they tend to exhibit overheads which lead to inefficiencies. An efficient security design flow (partially automatic) is presented here centered around Dynamic logic. The inefficiency problem of using dual-rail for either synchonous or asynchronous powerbalanced implementations can be resolved by steering towards alternative 1-of-n circuits [15] which use dynamic logic [16]. The aim here is to steer away from standard dual-rail circuits and move towards general N-nary 1-of-n circuits which use in addition to 1-of-2 circuits, direct mapping to 1-of-4 circuits [17]. Using dynamic logic it is possible to attain significant improvements in area and speed [18][19]. Another advantage of using 1-of-n as opposed to dual-rail encoding is that more complex codes offer the possibility of better energy efficiency [20]. The design flow that is presented here is focussed on cryptographic circuit generation and in particular Galois field implementation. A security specification is first entered using SystemC which undergoes various levels of refinement before sub-modules are generated. A novel logic library of specially designed power-balanced N-nary 1-of-n gates is provided. The dedicated dynamic gates from the new library, i.e. implicit-exor, exorhalf-implicit, etc., have been carefully designed to help reduce the area, delay and security of the implementation. The process is partially automated using a mapping algorithm to generate an optimal solution. Encoded balanced circuits, such as the above, are less prone to attack as there is less side-channel leakage. Correspondingly this makes security evaluation of these types of protected circuits less easy to evaluate. To overcome this a metric is provided which provides a measure of security based on the measure of degree by which the circuit is attackable. This is achieved using a measure which is derived from a combination of DPA and CPA measurements. This provides a measure of correlation which corresponds to the most likely points of attack. The higher the value provided by the metric the more likely a successful attack will be. The lower the value the less likely an attack will be successful. The metric enables us to evaluate the security of the generated circuits. The remainder of this paper is organised as follows: in section 2 we introduce our security metric; in section 3 we present the new library of 1-of-n encoded circuits; in section 4 we present our security design flow in section 5 we provide results and in section 6 conclusions are provided. 2 Power Analysis and Security metrics DPA is a side-channel attack which involves statistically analyzing power consumption measurements from a cryptosystem. In digital circuits there are effects correlated to data values being NCL-EECE-MSD-TR-2010-152, University of Newcastle Upon Tyne

IEEE Transactions on Computers, 2004

Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing ... more Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs will be more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal transition on a global interconnect is much greater than for internal wires in logic blocks. The paper addresses this issue by designing an asynchronous communication system aimed at power and pin efficiency. Another important issue of SoC design is design productivity. It demands new methods and tools, particularly for designing communication protocols and interconnects. The design of a self-timed communication system is approached employing formal techniques supported by verification and synthesis tools. The protocol is formally specified and verified with respect to deadlockfreedom and delay-insensitivity using a Petri-net-based model-checking tool. A protocol controller has been synthesized by a direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analyzed using the Cadence toolkit. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007

IEEE Journal of Solid-State Circuits, 2002

Synchronizer circuits are usually characterized by their rate of failure in transmitting data bet... more Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures

IEEE Transactions on Circuits and Systems I: Regular Papers, 2008

A novel self-timed communication protocol is based on the phase-modulation of a reference signal.... more A novel self-timed communication protocol is based on the phase-modulation of a reference signal. The reference signal is sent on a number of transmission lines and the data can be recovered observing the sequence of events on the these lines. Employing several lines increases the number of states hence reducing the number of symbols required for a transmission. A new encoding algorithm is described which generates symbol-dependent matrices which are used to control the phase of transmission lines. The protocol concept, the algorithm and analysis of the system, together with simulation results, are presented.

Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state ... more Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which have to be corrected manually. This paper presents a framework for an interactive refinement process aimed to help the designer. It is based on the visualization of conflict cores, i.e., sets of transitions causing coding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

Symposium on Asynchronous Circuits and Systems, 2000

The paper presents asynchronous design solutions to the problem of Priority Arbitration which is ... more The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined

Electronics Letters, 2007

ABSTRACT

2019 International Conference on Computing, Electronics & Communications Engineering (iCCECE)

Given the recent rise of the Internet-of-Things (IoT), networked devices are becoming deeply embe... more Given the recent rise of the Internet-of-Things (IoT), networked devices are becoming deeply embedded into everyday objects, leading to a need for novel security methods. Physical Unclonable Functions (PUFs) enable the differentiation between instances of the same device and have the potential to replace costly cryptographic operations while providing higher security guarantees, due to their inherent unclonability. We present a pairwise, continuous authentication protocol based on Physical Unclonable Functions (PUFs) and supporting mutual authentication on resource constrained nodes. The unclonability provided by the PUFs is an integral part of the authentication process to continuously prove the existence of the PUF secrets and the proposed protocol is executed periodically to enable the establishment of trust between the participants. This is achieved by refreshing the authentication information in every protocol round, leading to a ‘CRP Ratchet’ mechanism of renewing the authenticating PUF challenge response pairs (CRPs). We also discuss the security and performance of the protocol in IoT applications with a large number of devices. Since the only operations used in the periodic protocol phase are hashing and exclusive OR, low computation, complexity, and energy consumption overhead is achieved.

Lecture Notes in Computer Science

The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of ... more The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional

This paper presents a new design flow for security using 1-of-n encoding. Initially high-level Sy... more This paper presents a new design flow for security using 1-of-n encoding. Initially high-level SystemC Galois descriptions are compiled into an intermediate format. The design flow passes though several stages of refinement, including subfield-breakdown and change of basis, to generate small, regular logic blocks. These are converted into 1-of-n represention and subsequently passed to optimization and mapping tools for mapping to a new library of power-balanced components. The new library consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Finally logic optimization tools are applied to generate secure synchronous circuits for layout generation. The paper shows that the circuits generated are more efficient than those generated by alternative techniques.

Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The c... more Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The checker monitors the interface signals that follow a protocol. The checker produces a code word at its output when the interface signals abide to the protocol, where as, when the protocol is violated, a noncode word is generated at the output. Checkers are designed to directly implement sets of forbidden transitions, otherwise known as refusals. A “busy” approach is used to design the checker. In this approach, self-test of the checker is performed during the normal operation where the output signals are constantly switching.

ABSTRACT State coding conflict detection is a fundamental part of the synthesis of asynchronous c... more ABSTRACT State coding conflict detection is a fundamental part of the synthesis of asynchronous concurrent systems from their Signal Transition Graph (STG) specifications. This paper presents the extension of the method proposed earlier, the identification of state coding conflicts in STGs which is intended to work within a synthesis framework based on STG unfoldings. This approach has been implemented as a software tool using refined algorithms. A necessary condition detects state coding conflicts by using an approximate state covering approach. Being computationally efficient, this algorithm may generate false alarms. Thus a refinement technique is applied based on partial construction of the state space with extra computational cost. The experimental results demonstrating the efficiency of this approach are presented.