Alex Chow - Academia.edu (original) (raw)

Papers by Alex Chow

We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchr... more We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length, based on the initialization of the circuit. It also provides intrinsic fine-grain pipelining which alleviates the large feedback logic overhead in configurations with many taps, making such implementations practical. With an asynchronous-to-clocked interface, one can use the circuit in a synchronous environment. Detailed simulation results are presented.

I. INTRODUCTION CMOS-based sensors that precisely detect position and tilt benefit many mechanica... more I. INTRODUCTION CMOS-based sensors that precisely detect position and tilt benefit many mechanical and electronic systems, such as MEMS, robotic devices, instrumentation, and process control. Many existing sensor systems detect position and tilt through mechanical or ...

Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth,... more Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth, low-power, and low-latency chip-to-chip I/O. Chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits can send and receive signals through capacitive or inductive coupling. Packaging chips in this way, however, presents a number of physical challenges. The multi-chip package must hold and maintain the chips in precise alignment. This paper presents a number of electrical and mechanical technologies that address these challenges to enable multi-chip integration using Proximity Communication.

Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on ... more Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on a 36mum pitch. 144 channels operate simultaneously for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum CMOS. Measured energy consumption is 3.0pJ/b and BER is <10-15. Electronic alignment and crosstalk rejection allow reliable I/O for practical implementation

Flexible, stress-engineered spring interconnects is a novel technology potentially enabling room ... more Flexible, stress-engineered spring interconnects is a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solderfree technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. A dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each micro-spring site.

IEEE Journal of Solid-state Circuits, 2008

We present circuits for driving long on-chip wires through a series capacitor. The capacitor impr... more We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8X over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5X. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7X using a 200 mV swing.

A novel packaging approach has been demonstrated for circuits connected with flexible microspring... more A novel packaging approach has been demonstrated for circuits connected with flexible microsprings. The approach is based on silicon micromachined features and results in a highly accurate and low cost packaging solution. The micromachined features were processed into silicon with an anisotropic wet etch forming inverted pyramidal micro-pits. The pits are integrated into the chips along with arrays of flexible and compliant interconnects arranged in a daisy chain arrays on 180 µm pitch. Packages based on two chips with matching set of pits have been assembled and characterized. First level reliability tests have been performed in 0˚C-100˚C temperature cycling, 85/85 temperature humidity bias and high-current soak. Multiple "remating" tests were also carried out as the packages were taken apart and reassembled together. The "pit and spring" integration is expected to equally address not only the performance and functionality of the completed package but also its reliability and cost.

The migration towards multi-chip integration in microelectronic systems has motivated the use of ... more The migration towards multi-chip integration in microelectronic systems has motivated the use of on-chip sensors for in situ measurement of chip alignment, both at initial assembly and during system operation. This paper presents a CMOS position sensor that measures chip alignment by measuring differences in coupling capacitance. Unlike previous implementations, the present demonstration is immune to transistor leakage current, and can thus operate at high temperatures. A coherent detection scheme further lowers the noise floor, improving accuracy when the chips are far apart.

Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration an... more Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration and corresponding performance improvements in VLSI systems. However, fabrication costs present barriers to continued growth in transistor density. Proximity Communication breaks these barriers by providing high-density, high-bandwidth, low-power, and scalable off-chip I/O, allowing designers to partition their designs into separate chips with significantly reduced performance penalties. This partitioning

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series ... more Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwi... more Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examines existing ratios of bandwidth to execution rate versus memory capacity (or bytes/flop versus capacity ) found in a number of large-scale computers. The paper then explores a set of technologies, Proximity Communication, low-power on-chip networks, dense optical communication, and Sea-of-Anything interconnect, that can flatten this bandwidth hierarchy to relieve the memory bottleneck in a large-scale computer that we call "Hero."

We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchr... more We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length, based on the initialization of the circuit. It also provides intrinsic fine-grain pipelining which alleviates the large feedback logic overhead in configurations with many taps, making such implementations practical. With an asynchronous-to-clocked interface, one can use the circuit in a synchronous environment. Detailed simulation results are presented.

I. INTRODUCTION CMOS-based sensors that precisely detect position and tilt benefit many mechanica... more I. INTRODUCTION CMOS-based sensors that precisely detect position and tilt benefit many mechanical and electronic systems, such as MEMS, robotic devices, instrumentation, and process control. Many existing sensor systems detect position and tilt through mechanical or ...

Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth,... more Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth, low-power, and low-latency chip-to-chip I/O. Chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits can send and receive signals through capacitive or inductive coupling. Packaging chips in this way, however, presents a number of physical challenges. The multi-chip package must hold and maintain the chips in precise alignment. This paper presents a number of electrical and mechanical technologies that address these challenges to enable multi-chip integration using Proximity Communication.

Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on ... more Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on a 36mum pitch. 144 channels operate simultaneously for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum CMOS. Measured energy consumption is 3.0pJ/b and BER is <10-15. Electronic alignment and crosstalk rejection allow reliable I/O for practical implementation

Flexible, stress-engineered spring interconnects is a novel technology potentially enabling room ... more Flexible, stress-engineered spring interconnects is a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solderfree technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. A dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each micro-spring site.

IEEE Journal of Solid-state Circuits, 2008

We present circuits for driving long on-chip wires through a series capacitor. The capacitor impr... more We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8X over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5X. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7X using a 200 mV swing.

A novel packaging approach has been demonstrated for circuits connected with flexible microspring... more A novel packaging approach has been demonstrated for circuits connected with flexible microsprings. The approach is based on silicon micromachined features and results in a highly accurate and low cost packaging solution. The micromachined features were processed into silicon with an anisotropic wet etch forming inverted pyramidal micro-pits. The pits are integrated into the chips along with arrays of flexible and compliant interconnects arranged in a daisy chain arrays on 180 µm pitch. Packages based on two chips with matching set of pits have been assembled and characterized. First level reliability tests have been performed in 0˚C-100˚C temperature cycling, 85/85 temperature humidity bias and high-current soak. Multiple "remating" tests were also carried out as the packages were taken apart and reassembled together. The "pit and spring" integration is expected to equally address not only the performance and functionality of the completed package but also its reliability and cost.

The migration towards multi-chip integration in microelectronic systems has motivated the use of ... more The migration towards multi-chip integration in microelectronic systems has motivated the use of on-chip sensors for in situ measurement of chip alignment, both at initial assembly and during system operation. This paper presents a CMOS position sensor that measures chip alignment by measuring differences in coupling capacitance. Unlike previous implementations, the present demonstration is immune to transistor leakage current, and can thus operate at high temperatures. A coherent detection scheme further lowers the noise floor, improving accuracy when the chips are far apart.

Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration an... more Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration and corresponding performance improvements in VLSI systems. However, fabrication costs present barriers to continued growth in transistor density. Proximity Communication breaks these barriers by providing high-density, high-bandwidth, low-power, and scalable off-chip I/O, allowing designers to partition their designs into separate chips with significantly reduced performance penalties. This partitioning

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series ... more Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwi... more Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examines existing ratios of bandwidth to execution rate versus memory capacity (or bytes/flop versus capacity ) found in a number of large-scale computers. The paper then explores a set of technologies, Proximity Communication, low-power on-chip networks, dense optical communication, and Sea-of-Anything interconnect, that can flatten this bandwidth hierarchy to relieve the memory bottleneck in a large-scale computer that we call "Hero."