Alexander Fish - Academia.edu (original) (raw)

Papers by Alexander Fish

This paper presents implementation of a low-power tracking CMOS image sensor based on biological ... more This paper presents implementation of a low-power tracking CMOS image sensor based on biological models of attention. The presented imager allows tracking of up to N salient targets in the field of view. Employing "smart" image sensor architecture, where all image processing is implemented on the sensor focal plane, the proposed imager allows reduction of the amount of data transmitted

IEEE Transactions on Circuits and Systems I: Regular Papers, 2016

Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high... more Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high density, low bitcell leakage, logic compatibility, and suitability for 2-port memories. The major drawbacks of GC-eDRAMs are their limited data retention times (RTs) and the large spread of RT across an array, which degrade energy-efficiency due to refresh cycles. While the array refresh rate can be determined according to circuit simulation or post-manufacturing calibration, there is a lack of analytical and statistical RT models for GC-eDRAM that could unveil the limiters and circuit parameters that lead to the large observed RT spreads. In this work, we derive the first comprehensive analytical model for the statistical distribution of the per-cell retention time of 2T-bitcell GC-eDRAMs, which is found to follow a log-normal distribution. The accuracy of the proposed retention time model is verified by extensive Monte Carlo and worst case distance circuit simulations and silicon measurements of an 0.18 μm test chip. Furthermore, a sensitivity analysis unveils the circuit parameters that have the highest impact on the RT spread. Interestingly, the variability of the threshold voltage of the write access transistor has a much higher impact on the RT spread than the variability of any other circuit parameter, including the storage node capacitor. This holds true under process scaling, for nodes as advanced as 28 nm, as shown through simulation. The insights gained from the retention time model help circuit designers achieve better GC-eDRAMs with longer RTs and sharper RT distributions. In addition, the herein presented model can be used as a basis to study the reliability/energy trade-off for GC-eDRAM usage in fault-tolerant VLSI systems.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applica... more Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32×32 bit memory macro was designed and fabricated in a standard 0.18-µm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRA... more Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as non-trivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability to conventional GC structures. The proposed circuit is demonstrated with a 2 kb memory macro that was designed and fabricated in a mature 0.18 µm CMOS process, targeted at low-power, energyefficient applications. The test array is powered with a single supply of 900 mV, showing an 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43%, as compared to a redrawn 6T SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

Journal of Low Power Electronics and Applications, 2013

Ultra-low power applications often require several kb of embedded memory and are typically operat... more Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (V DD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-V T) domain. Minimum V DD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 µm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum V DD. We find that an 0.18 µm gain-cell array can be robustly operated at a sub-V T supply voltage of 400 mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality J. Low Power Electron. Appl. 2013, 3 55 under parametric variations. As opposed to sub-V T operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600 mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell's retention time. Monte Carlo simulations show that a 600 mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to trad... more Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65 nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.

2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012

Biomedical systems often require several kb of embedded memory and are typically operated in the ... more Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, lowleakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 10 4 times higher than the access time. Monte Carlos simulations show that the 2 kb gaincell array, implemented in a mature 0.18 µm CMOS node and supplied with a sub-VT voltage of 400 mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.

Journal of Low Power Electronics and Applications, 2011

A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been propos... more A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been proposed throughout the years. These solutions can be categorized into different groups according to the principle used for DR widening. One of the methods, which is based on autonomous control over the integration time, was implemented by our group. We proposed the multiple resets algorithm, which was successfully implemented in three generations of WDR image sensors. While achieving the same goal of widening the DR of the sensor, each of the implemented imagers had a different architecture, and therefore presented different performance and power figures. This paper reviews designs of the aforementioned sensors and presents a comprehensive analysis of their power consumption. Power-performance tradeoffs are also discussed. Advantages and disadvantages of each sensor are presented.

2009 IEEE International Symposium on Circuits and Systems, 2009

ABSTRACT In recent years, low power design has become one of the main focuses of digital VLSI cir... more ABSTRACT In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing flip-flop cells, designed to operate in the subthreshold region. Both cells integrate a gate-diffusion input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the flip-flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90 nm process achieving a power dissipation of 8.4 nW in a typical corner at VDD = 300 mV with a delay of 51.7 nsec.

Sensors (Basel, Switzerland), 2012

Modern "smart" CMOS sensors have penetrated into various applications, such as surveill... more Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation...

2009 IEEE Sensors, 2009

Static leakage power is the major component of power consumption in large arrays that operate at ... more Static leakage power is the major component of power consumption in large arrays that operate at a low activity factor. “Smart” image sensors with advanced in-pixel functionality frequently include large on-chip memory arrays for storage of per-pixel data. These systems periodically transfer data from pixels to their corresponding memory bits in a serial access scheme with a relatively low activity factor. Recently, an Adaptive Bulk Biasing Control (AB2C) Scheme for leakage reduction in image sensors was presented. In this paper, we introduce an improved AB2C scheme that expands the functionality for on-chip memory leakage reduction, in addition to that of the image sensor. In the proposed system, a symmetric voltage distribution is applied around the active row, providing reverse body biasing on deactivated rows to reduce leakage. A test case circuit was implemented in a standard 90nm TSMC process is presented, showing a static power reduction of 26%.

The Journal of Engineering, 2013

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density altern... more Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain-cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain-cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.

2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), 2014

Technology advancements in recent years have led to an increase in the employment of integrated c... more Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65 nm CMOS process under slightly scaled supply voltages.

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 2012

With the increasing requirement of a high-density, high-performance, low-power alternative to tra... more With the increasing requirement of a high-density, high-performance, low-power alternative to traditional SRAM, Gain Cell (GC) embedded DRAMs have gained a renewed interest in recent years. Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and biomedical system storage. In this paper, we review and compare the recent publications, examining the design requirements and the implementation techniques that lead to achievement of the required design metrics of these applications.

Journal of Low Power Electronics and Applications, 2011

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in ad... more As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

2008 IEEE International Symposium on Circuits and Systems, 2008

ABSTRACT An autonomous image sensor for real time target detection and tracking is presented. The... more ABSTRACT An autonomous image sensor for real time target detection and tracking is presented. The sensor is based on a CMOS APS array, equipped with in-pixel functionality and integrates analog and digital components to achieve autonomous operation with minimal power dissipation. The system employs a two-phased operation flow; during the initial acquisition stage, the digital controller detects and acquires the brightest targets in the field of view within a single frame and defines windows of interest (WOI) around the center of mass coordinates of each object. Subsequently, the system moves into the analog tracking mode during which all areas outside of the WOI are entirely shut down, thus saving power to a number of orders of magnitude. In addition to its low power dissipation, the sensor features real-time operation, low fixed pattern noise, linearity and the ability to track a predefined number of targets throughout the entire field of view. A 64times64 pixel sensor array has been designed in 0.18 mum CMOS technology and is operated via a 1.8 V supply. The imager architecture is discussed, the circuits' descriptions are shown and simulation results are presented.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2014

A novel Dual Mode Square adder is proposed. The adder achieves low energy, high performance and s... more A novel Dual Mode Square adder is proposed. The adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD.

IEEE Journal of Solid-State Circuits, 2014

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag ... more The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 µm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the "5-cent RFID tag" become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm 2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 µW, which is sufficiently supplied by the on-chip energy harvesting unit.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT One of the main obstacles delaying a more widespread use of radio frequency identificati... more ABSTRACT One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18µm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8µW during operation cycles.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-l... more ABSTRACT A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low power low cost option for embedded RFID design. This cell requires the application of a 10V potential difference between the cell's control lines for program and erase operations. Providing the required voltages includes several challenges in the design of the voltage driver, such as the elimination of Gate Induced Drain Leakage (GIDL) currents. In this paper, we present a voltage driver architecture that utilizes novel techniques to overcome the power consumption problems during high voltage propagation. This driver was implemented in the TowerJazz 0.18μm CMOS technology, providing the required functionality with a low static-power figure of 34.6pW.

This paper presents implementation of a low-power tracking CMOS image sensor based on biological ... more This paper presents implementation of a low-power tracking CMOS image sensor based on biological models of attention. The presented imager allows tracking of up to N salient targets in the field of view. Employing "smart" image sensor architecture, where all image processing is implemented on the sensor focal plane, the proposed imager allows reduction of the amount of data transmitted

IEEE Transactions on Circuits and Systems I: Regular Papers, 2016

Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high... more Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high density, low bitcell leakage, logic compatibility, and suitability for 2-port memories. The major drawbacks of GC-eDRAMs are their limited data retention times (RTs) and the large spread of RT across an array, which degrade energy-efficiency due to refresh cycles. While the array refresh rate can be determined according to circuit simulation or post-manufacturing calibration, there is a lack of analytical and statistical RT models for GC-eDRAM that could unveil the limiters and circuit parameters that lead to the large observed RT spreads. In this work, we derive the first comprehensive analytical model for the statistical distribution of the per-cell retention time of 2T-bitcell GC-eDRAMs, which is found to follow a log-normal distribution. The accuracy of the proposed retention time model is verified by extensive Monte Carlo and worst case distance circuit simulations and silicon measurements of an 0.18 μm test chip. Furthermore, a sensitivity analysis unveils the circuit parameters that have the highest impact on the RT spread. Interestingly, the variability of the threshold voltage of the write access transistor has a much higher impact on the RT spread than the variability of any other circuit parameter, including the storage node capacitor. This holds true under process scaling, for nodes as advanced as 28 nm, as shown through simulation. The insights gained from the retention time model help circuit designers achieve better GC-eDRAMs with longer RTs and sharper RT distributions. In addition, the herein presented model can be used as a basis to study the reliability/energy trade-off for GC-eDRAM usage in fault-tolerant VLSI systems.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applica... more Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32×32 bit memory macro was designed and fabricated in a standard 0.18-µm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRA... more Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as non-trivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability to conventional GC structures. The proposed circuit is demonstrated with a 2 kb memory macro that was designed and fabricated in a mature 0.18 µm CMOS process, targeted at low-power, energyefficient applications. The test array is powered with a single supply of 900 mV, showing an 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43%, as compared to a redrawn 6T SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

Journal of Low Power Electronics and Applications, 2013

Ultra-low power applications often require several kb of embedded memory and are typically operat... more Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (V DD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-V T) domain. Minimum V DD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 µm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum V DD. We find that an 0.18 µm gain-cell array can be robustly operated at a sub-V T supply voltage of 400 mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality J. Low Power Electron. Appl. 2013, 3 55 under parametric variations. As opposed to sub-V T operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600 mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell's retention time. Monte Carlo simulations show that a 600 mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz.

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to trad... more Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65 nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.

2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012

Biomedical systems often require several kb of embedded memory and are typically operated in the ... more Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, lowleakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 10 4 times higher than the access time. Monte Carlos simulations show that the 2 kb gaincell array, implemented in a mature 0.18 µm CMOS node and supplied with a sub-VT voltage of 400 mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.

Journal of Low Power Electronics and Applications, 2011

A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been propos... more A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been proposed throughout the years. These solutions can be categorized into different groups according to the principle used for DR widening. One of the methods, which is based on autonomous control over the integration time, was implemented by our group. We proposed the multiple resets algorithm, which was successfully implemented in three generations of WDR image sensors. While achieving the same goal of widening the DR of the sensor, each of the implemented imagers had a different architecture, and therefore presented different performance and power figures. This paper reviews designs of the aforementioned sensors and presents a comprehensive analysis of their power consumption. Power-performance tradeoffs are also discussed. Advantages and disadvantages of each sensor are presented.

2009 IEEE International Symposium on Circuits and Systems, 2009

ABSTRACT In recent years, low power design has become one of the main focuses of digital VLSI cir... more ABSTRACT In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing flip-flop cells, designed to operate in the subthreshold region. Both cells integrate a gate-diffusion input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the flip-flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90 nm process achieving a power dissipation of 8.4 nW in a typical corner at VDD = 300 mV with a delay of 51.7 nsec.

Sensors (Basel, Switzerland), 2012

Modern "smart" CMOS sensors have penetrated into various applications, such as surveill... more Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation...

2009 IEEE Sensors, 2009

Static leakage power is the major component of power consumption in large arrays that operate at ... more Static leakage power is the major component of power consumption in large arrays that operate at a low activity factor. “Smart” image sensors with advanced in-pixel functionality frequently include large on-chip memory arrays for storage of per-pixel data. These systems periodically transfer data from pixels to their corresponding memory bits in a serial access scheme with a relatively low activity factor. Recently, an Adaptive Bulk Biasing Control (AB2C) Scheme for leakage reduction in image sensors was presented. In this paper, we introduce an improved AB2C scheme that expands the functionality for on-chip memory leakage reduction, in addition to that of the image sensor. In the proposed system, a symmetric voltage distribution is applied around the active row, providing reverse body biasing on deactivated rows to reduce leakage. A test case circuit was implemented in a standard 90nm TSMC process is presented, showing a static power reduction of 26%.

The Journal of Engineering, 2013

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density altern... more Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain-cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain-cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.

2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), 2014

Technology advancements in recent years have led to an increase in the employment of integrated c... more Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65 nm CMOS process under slightly scaled supply voltages.

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 2012

With the increasing requirement of a high-density, high-performance, low-power alternative to tra... more With the increasing requirement of a high-density, high-performance, low-power alternative to traditional SRAM, Gain Cell (GC) embedded DRAMs have gained a renewed interest in recent years. Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and biomedical system storage. In this paper, we review and compare the recent publications, examining the design requirements and the implementation techniques that lead to achievement of the required design metrics of these applications.

Journal of Low Power Electronics and Applications, 2011

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in ad... more As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

2008 IEEE International Symposium on Circuits and Systems, 2008

ABSTRACT An autonomous image sensor for real time target detection and tracking is presented. The... more ABSTRACT An autonomous image sensor for real time target detection and tracking is presented. The sensor is based on a CMOS APS array, equipped with in-pixel functionality and integrates analog and digital components to achieve autonomous operation with minimal power dissipation. The system employs a two-phased operation flow; during the initial acquisition stage, the digital controller detects and acquires the brightest targets in the field of view within a single frame and defines windows of interest (WOI) around the center of mass coordinates of each object. Subsequently, the system moves into the analog tracking mode during which all areas outside of the WOI are entirely shut down, thus saving power to a number of orders of magnitude. In addition to its low power dissipation, the sensor features real-time operation, low fixed pattern noise, linearity and the ability to track a predefined number of targets throughout the entire field of view. A 64times64 pixel sensor array has been designed in 0.18 mum CMOS technology and is operated via a 1.8 V supply. The imager architecture is discussed, the circuits' descriptions are shown and simulation results are presented.

IEEE Transactions on Circuits and Systems I: Regular Papers, 2014

A novel Dual Mode Square adder is proposed. The adder achieves low energy, high performance and s... more A novel Dual Mode Square adder is proposed. The adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD.

IEEE Journal of Solid-State Circuits, 2014

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag ... more The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 µm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the "5-cent RFID tag" become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm 2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 µW, which is sufficiently supplied by the on-chip energy harvesting unit.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT One of the main obstacles delaying a more widespread use of radio frequency identificati... more ABSTRACT One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18µm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8µW during operation cycles.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-l... more ABSTRACT A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low power low cost option for embedded RFID design. This cell requires the application of a 10V potential difference between the cell's control lines for program and erase operations. Providing the required voltages includes several challenges in the design of the voltage driver, such as the elimination of Gate Induced Drain Leakage (GIDL) currents. In this paper, we present a voltage driver architecture that utilizes novel techniques to overcome the power consumption problems during high voltage propagation. This driver was implemented in the TowerJazz 0.18μm CMOS technology, providing the required functionality with a low static-power figure of 34.6pW.