Alexander Nadel - Academia.edu (original) (raw)

Papers by Alexander Nadel

Research paper thumbnail of Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization

2019 Formal Methods in Computer Aided Design (FMCAD), 2019

Research paper thumbnail of Boosting Minimal Unsatisfiable Core Extraction

Research paper thumbnail of Understanding and Improving a Modern SAT Solver

Propositional satisfiability (SAT) is an NP-complete problem, holding a central place in computer... more Propositional satisfiability (SAT) is an NP-complete problem, holding a central place in computer science and engineering. SAT has numerous applications in formal verification, artificial intelligence and other areas. Modern SAT solvers, using an enhanced version of the backtrack search DavisLogemann-Loveland (DLL) algorithm, are able to successfully cope with instances comprising millions of variables. This work is an attempt to shed new light on the functionality of a modern SAT solver. We also propose a number of enhancements that are empirically useful, especially in the formal verification domain. We propose a framework for presenting and analyzing a modern DLLbased SAT solver. We provide a basic backtracking algorithm that explicitly shows the process of resolution refutation construction. Our approach is based on the notion of a parent resolution derivation – a resolution proof for validness of a flip operation. We show how to derive the algorithm of a modern SAT solver from basic backtracking step-by-step. This resolution-based approach allows us to define new criteria for measuring the practical impact of different schemes for conflict-driven learning by making the notion of search pruning more formal. We show that the 1UIP scheme, enhanced by conflict clause minimization, is better than other known schemes in terms of pruning. This explains its empirical advantage over other schemes. We propose an enhancement to the minimized 1UIP scheme, called local conflict clause recording. This technique improves the performance of a modern SAT solver by recording additional conflict clauses. Local conflict clause recording makes the learning less dependent on the variable polarity selection heuristic. Assignment stack shrinking is a technique whose goal is to shrink the size of the assignment stack and conflict clauses. We demonstrate the empirical usefulness of assignment stack shrinking and analyze its impact on the performance of a modern SAT solver, comparing it to the impact of conflict clause minimization and rapid restarts. Furthermore, a new decision heuristic for SAT, called the clause-based heuristic, is introduced. This heuristic is designed to increase the likelihood that interrelated variables will be chosen in proximity. It maintains a clause list containing both the initial and conflict clauses. The next decision literal is picked from the first unsatisfied clause. We propose various methods for initially organizing the clause list and for moving clauses within it. Our approach results in a significant performance boost over existing heuristics tested on hard real-world industrial benchmarks. Finally, we present an algorithm for minimal unsatisfiable core extraction that is able to find a minimal unsatisfiable core for large real-world formulas. Benchmark families, arising in formal verification of hardware, are of particular interest to us. Modern SAT solvers are able to produce a resolution refutation of a given unsatisfiable formula, whose sources are the input clauses and whose sink is the empty clause. Our method’s basic version removes the input clauses connected to the empty clause one by one from the resolution refutation, preserving the validity of the refutation by adding other clauses and resolution relations until no more input clauses can be removed. In the end, all the input clauses, connected to the empty clause, comprise the minimal unsatisfiable core.

Research paper thumbnail of Designers Work Less with Quality Formal Equivalence Checking

Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schema... more Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schematics implementation against a golden RTL model. This equivalence must be guaranteed in light of possible multiple local hand-implemented changes in the schematics. To overcome capacity problems, FEC is usually performed on system sub-blocks, whereas the “environment ” is modeled with assumptions written using a property specification language such as SVA. These assumptions must later be proved relative to the driving logic. The majority of FEC tools today are based on SAT-based model checking formal verification engines. In this paper, we describe an approach that can considerably reduce both the time and computational effort required to complete FEC activity in a project. It is based on an additional step introduced to complement the traditional SAT-based model checking algorithm. This step calculates a minimal set of required assumptions using a new SAT-based algorithm. Minimizing the ...

Research paper thumbnail of Understanding and Improving a Modern

Research paper thumbnail of Solving MaxSAT with Bit-Vector Optimization

Theory and Applications of Satisfiability Testing – SAT 2018, 2018

Research paper thumbnail of Solving linear arithmetic with SAT-based model checking

2017 Formal Methods in Computer Aided Design (FMCAD), 2017

Research paper thumbnail of Polarity and Variable Selection Heuristics for SAT-Based Anytime MaxSAT

Journal on Satisfiability, Boolean Modeling and Computation, 2020

This paper is a system description of the anytime MaxSAT solver TT-Open-WBO-Inc, which won both o... more This paper is a system description of the anytime MaxSAT solver TT-Open-WBO-Inc, which won both of the weighted incomplete tracks of MaxSAT Evaluation 2019. We implemented the recently introduced polarity and variable selection heuristics, TORC and TSB, respectively, in the Open-WBO-Inc-BMO algorithm within the open-source anytime MaxSAT solver Open-WBO-Inc. As a result, the solver is substantially more efficient.

Research paper thumbnail of Handling Bit-Propagating Operations in Bit-Vector Reasoning

Our aim is to improve bit-vector reasoning in modern SMT solvers. We enhance bitvector preprocess... more Our aim is to improve bit-vector reasoning in modern SMT solvers. We enhance bitvector preprocessing by introducing algorithms that explicitly handle an important class of bit-vector operations which we call bit-propagating. Such operations fulfill the following property: each output bit is either a bit of one of the inputs or a constant (0 or 1). We identified ten bit-propagating operations in the SMT-LIB 2.0 language; these operations are encountered frequently in practice. Our algorithms seek to improve the run-time of SMT solvers by simplifying the problem that is eventually provided to the underlying SAT solver. Empirical evaluation of our algorithms reveals a performance boost across a variety of SMT-LIB benchmark families.

Research paper thumbnail of A Lazy and Layered SMT ( B V ) Solver for Hard Industrial Verification Problems ⋆

Rarely verification problems originate from bit-level desc riptions. Yet, most of the verificatio... more Rarely verification problems originate from bit-level desc riptions. Yet, most of the verification technologies are based on bit blasting, i.e., reduction to boolean reasoning. In this paper we advocate reasoning at higher level of abstra ction, within the theory of bit vectors ( B V ), where structural information (e.g. equalities, arithme tic functions) is not blasted into bits. Our approach relies on t he lazy Satisfiability Modulo Theories (SMT) paradigm. We developed a satisfiabili ty procedure for reasoning about bit vectors that carefully leverages on the power of boolean SAT solver to deal with components that are more naturally “bool ean”, and activates bit-vector reasoning whenever possible. The procedure has two distinguishing features. First, it relies on the on-line integration of a SA T solver with an incremental and backtrackable solver for B V that enables dynamical optimization of the reasoning about bit vectors; for instance, this is an imp rovement over static enc...

Research paper thumbnail of Anytime Algorithms for MaxSAT and Beyond

2020 Formal Methods in Computer Aided Design (FMCAD), 2020

Given a propositional formula FFF in Conjunctive Normal Form (CNF), a SAT solver decides whether ... more Given a propositional formula FFF in Conjunctive Normal Form (CNF), a SAT solver decides whether it is satisfiable or not. It is often required to find a solution to a satisfiable CNF formula F, which optimizes a given Pseudo-Boolean objective function Ψ, that is, to extend SAT to optimization. MaxSAT is a widely used extension of SAT to optimization. A MaxSAT solver can be applied to optimize a Pseudo-Boolean objective function Ψ, given a CNF formula F, whenever Ψ is a linear function. MaxSAT has a diverse plethora of applications, including applications in computer-aided design, artificial intelligence, planning, scheduling and bioinformatics. A variety of approaches to MaxSAT have been developed over the last two decades. In this tutorial, we focus on anytime MaxSAT algorithms, where an anytime algorithm is expected to find better and better solutions, the longer it keeps running. The anytime property is crucial in industrial applications, since it allows the user to: 1) get an a...

Research paper thumbnail of Is Bit-Vector Reasoning as Hard as NExpTime in Practice ? ( Extended Abstract )

It has been shown that quantifier-free bit-vector logic (QF BV) is NExpTime-complete, on account ... more It has been shown that quantifier-free bit-vector logic (QF BV) is NExpTime-complete, on account of the fact that the number of propositional variables in the SAT encoding of a QF BV formula grows exponentially with the length of the declarations of the bit-vector variables in the input formula. This level of complexity is surprising, given that in practice QF BV is being used successfully in a wide range of applications. This work points out that the high complexity does not necessary hold in practical applications of QF BV. We give two examples of easier families of QF BV problems. First, we demonstrate that, in a recent critical Intel application of QF BV in clock routing, the number of propositional variables grows polynomially with the length of the variable declarations, thus establishing that clock routing uses an NP-complete subset of QF BV. Second, we show that in another application, namely, microcode validation, register width should be viewed as a fixed parameter (more p...

Research paper thumbnail of On Optimizing a Generic Function in SAT

The goal of this study is to improve the scalability of today's SAT-based solutions for optim... more The goal of this study is to improve the scalability of today's SAT-based solutions for optimization problems and to pave the way towards extending the range of optimization problems solvable with SAT in practice. Let OptSAT be the problem of optimizing a generic Pseudo-Boolean function, given a satisfiable propositional formula F. We introduce an incremental and anytime incomplete algorithm for solving OptSAT, called Polosat. We show that integrating Polosat into a state-of-the-art open-source anytime MaxSAT solver significantly improves the solver's performance. Furthermore, we demonstrate that Polosat substantially improves the solution quality of an industrial placement tool, where placement is a sub-stage of the physical design stage of chip design.

Research paper thumbnail of From Total Assignment Enumeration to Modern SAT Solver

ArXiv, 2011

A new framework for presenting and analyzing the functionality of a modern DLL-based SAT solver i... more A new framework for presenting and analyzing the functionality of a modern DLL-based SAT solver is proposed. Our approach exploits the inherent relation between backtracking and resolution. We show how to derive the algorithm of a modern SAT solver from DLL step-by-step. We analyze the inference power of Boolean Constraint Propagation, Non-Chronological Backtracking and 1UIP-based Conflict-Directed Backjumping. Our work can serve as an introduction to a modern SAT solver functionality and as a basis for future work on the inference power of a modern SAT solver and on practical SAT solver design.

Research paper thumbnail of Routing under constraints

2016 Formal Methods in Computer-Aided Design (FMCAD), 2016

Research paper thumbnail of A Correct-by-Decision Solution for Simultaneous Place and Route

Computer Aided Verification, 2017

Research paper thumbnail of Bit-Vector Optimization

Tools and Algorithms for the Construction and Analysis of Systems, 2016

Research paper thumbnail of Local Search with a SAT Oracle for Combinatorial Optimization

NP-hard combinatorial optimization problems are pivotal in science and business. There exists a v... more NP-hard combinatorial optimization problems are pivotal in science and business. There exists a variety of approaches for solving such problems, but for problems with complex constraints and objective functions, local search algorithms scale the best. Such algorithms usually assume that finding a non-optimal solution with no other requirements is easy. However, what if it is NP-hard? In such case, a SAT solver can be used for finding the initial solution, but how can one continue solving the optimization problem? We offer a generic methodology, called Local Search with SAT Oracle (LSSO), to solve such problems. LSSO facilitates implementation of advanced local search methods, such as variable neighbourhood search, hill climbing and iterated local search, while using a SAT solver as an oracle. We have successfully applied our approach to solve a critical industrial problem of cell placement and productized our solution at Intel.

Research paper thumbnail of Chronological Backtracking

Theory and Applications of Satisfiability Testing – SAT 2018, 2018

Research paper thumbnail of Accelerated Deletion-based Extraction of Minimal Unsatisfiable Cores

Journal on Satisfiability, Boolean Modeling and Computation, 2014

Research paper thumbnail of Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization

2019 Formal Methods in Computer Aided Design (FMCAD), 2019

Research paper thumbnail of Boosting Minimal Unsatisfiable Core Extraction

Research paper thumbnail of Understanding and Improving a Modern SAT Solver

Propositional satisfiability (SAT) is an NP-complete problem, holding a central place in computer... more Propositional satisfiability (SAT) is an NP-complete problem, holding a central place in computer science and engineering. SAT has numerous applications in formal verification, artificial intelligence and other areas. Modern SAT solvers, using an enhanced version of the backtrack search DavisLogemann-Loveland (DLL) algorithm, are able to successfully cope with instances comprising millions of variables. This work is an attempt to shed new light on the functionality of a modern SAT solver. We also propose a number of enhancements that are empirically useful, especially in the formal verification domain. We propose a framework for presenting and analyzing a modern DLLbased SAT solver. We provide a basic backtracking algorithm that explicitly shows the process of resolution refutation construction. Our approach is based on the notion of a parent resolution derivation – a resolution proof for validness of a flip operation. We show how to derive the algorithm of a modern SAT solver from basic backtracking step-by-step. This resolution-based approach allows us to define new criteria for measuring the practical impact of different schemes for conflict-driven learning by making the notion of search pruning more formal. We show that the 1UIP scheme, enhanced by conflict clause minimization, is better than other known schemes in terms of pruning. This explains its empirical advantage over other schemes. We propose an enhancement to the minimized 1UIP scheme, called local conflict clause recording. This technique improves the performance of a modern SAT solver by recording additional conflict clauses. Local conflict clause recording makes the learning less dependent on the variable polarity selection heuristic. Assignment stack shrinking is a technique whose goal is to shrink the size of the assignment stack and conflict clauses. We demonstrate the empirical usefulness of assignment stack shrinking and analyze its impact on the performance of a modern SAT solver, comparing it to the impact of conflict clause minimization and rapid restarts. Furthermore, a new decision heuristic for SAT, called the clause-based heuristic, is introduced. This heuristic is designed to increase the likelihood that interrelated variables will be chosen in proximity. It maintains a clause list containing both the initial and conflict clauses. The next decision literal is picked from the first unsatisfied clause. We propose various methods for initially organizing the clause list and for moving clauses within it. Our approach results in a significant performance boost over existing heuristics tested on hard real-world industrial benchmarks. Finally, we present an algorithm for minimal unsatisfiable core extraction that is able to find a minimal unsatisfiable core for large real-world formulas. Benchmark families, arising in formal verification of hardware, are of particular interest to us. Modern SAT solvers are able to produce a resolution refutation of a given unsatisfiable formula, whose sources are the input clauses and whose sink is the empty clause. Our method’s basic version removes the input clauses connected to the empty clause one by one from the resolution refutation, preserving the validity of the refutation by adding other clauses and resolution relations until no more input clauses can be removed. In the end, all the input clauses, connected to the empty clause, comprise the minimal unsatisfiable core.

Research paper thumbnail of Designers Work Less with Quality Formal Equivalence Checking

Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schema... more Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schematics implementation against a golden RTL model. This equivalence must be guaranteed in light of possible multiple local hand-implemented changes in the schematics. To overcome capacity problems, FEC is usually performed on system sub-blocks, whereas the “environment ” is modeled with assumptions written using a property specification language such as SVA. These assumptions must later be proved relative to the driving logic. The majority of FEC tools today are based on SAT-based model checking formal verification engines. In this paper, we describe an approach that can considerably reduce both the time and computational effort required to complete FEC activity in a project. It is based on an additional step introduced to complement the traditional SAT-based model checking algorithm. This step calculates a minimal set of required assumptions using a new SAT-based algorithm. Minimizing the ...

Research paper thumbnail of Understanding and Improving a Modern

Research paper thumbnail of Solving MaxSAT with Bit-Vector Optimization

Theory and Applications of Satisfiability Testing – SAT 2018, 2018

Research paper thumbnail of Solving linear arithmetic with SAT-based model checking

2017 Formal Methods in Computer Aided Design (FMCAD), 2017

Research paper thumbnail of Polarity and Variable Selection Heuristics for SAT-Based Anytime MaxSAT

Journal on Satisfiability, Boolean Modeling and Computation, 2020

This paper is a system description of the anytime MaxSAT solver TT-Open-WBO-Inc, which won both o... more This paper is a system description of the anytime MaxSAT solver TT-Open-WBO-Inc, which won both of the weighted incomplete tracks of MaxSAT Evaluation 2019. We implemented the recently introduced polarity and variable selection heuristics, TORC and TSB, respectively, in the Open-WBO-Inc-BMO algorithm within the open-source anytime MaxSAT solver Open-WBO-Inc. As a result, the solver is substantially more efficient.

Research paper thumbnail of Handling Bit-Propagating Operations in Bit-Vector Reasoning

Our aim is to improve bit-vector reasoning in modern SMT solvers. We enhance bitvector preprocess... more Our aim is to improve bit-vector reasoning in modern SMT solvers. We enhance bitvector preprocessing by introducing algorithms that explicitly handle an important class of bit-vector operations which we call bit-propagating. Such operations fulfill the following property: each output bit is either a bit of one of the inputs or a constant (0 or 1). We identified ten bit-propagating operations in the SMT-LIB 2.0 language; these operations are encountered frequently in practice. Our algorithms seek to improve the run-time of SMT solvers by simplifying the problem that is eventually provided to the underlying SAT solver. Empirical evaluation of our algorithms reveals a performance boost across a variety of SMT-LIB benchmark families.

Research paper thumbnail of A Lazy and Layered SMT ( B V ) Solver for Hard Industrial Verification Problems ⋆

Rarely verification problems originate from bit-level desc riptions. Yet, most of the verificatio... more Rarely verification problems originate from bit-level desc riptions. Yet, most of the verification technologies are based on bit blasting, i.e., reduction to boolean reasoning. In this paper we advocate reasoning at higher level of abstra ction, within the theory of bit vectors ( B V ), where structural information (e.g. equalities, arithme tic functions) is not blasted into bits. Our approach relies on t he lazy Satisfiability Modulo Theories (SMT) paradigm. We developed a satisfiabili ty procedure for reasoning about bit vectors that carefully leverages on the power of boolean SAT solver to deal with components that are more naturally “bool ean”, and activates bit-vector reasoning whenever possible. The procedure has two distinguishing features. First, it relies on the on-line integration of a SA T solver with an incremental and backtrackable solver for B V that enables dynamical optimization of the reasoning about bit vectors; for instance, this is an imp rovement over static enc...

Research paper thumbnail of Anytime Algorithms for MaxSAT and Beyond

2020 Formal Methods in Computer Aided Design (FMCAD), 2020

Given a propositional formula FFF in Conjunctive Normal Form (CNF), a SAT solver decides whether ... more Given a propositional formula FFF in Conjunctive Normal Form (CNF), a SAT solver decides whether it is satisfiable or not. It is often required to find a solution to a satisfiable CNF formula F, which optimizes a given Pseudo-Boolean objective function Ψ, that is, to extend SAT to optimization. MaxSAT is a widely used extension of SAT to optimization. A MaxSAT solver can be applied to optimize a Pseudo-Boolean objective function Ψ, given a CNF formula F, whenever Ψ is a linear function. MaxSAT has a diverse plethora of applications, including applications in computer-aided design, artificial intelligence, planning, scheduling and bioinformatics. A variety of approaches to MaxSAT have been developed over the last two decades. In this tutorial, we focus on anytime MaxSAT algorithms, where an anytime algorithm is expected to find better and better solutions, the longer it keeps running. The anytime property is crucial in industrial applications, since it allows the user to: 1) get an a...

Research paper thumbnail of Is Bit-Vector Reasoning as Hard as NExpTime in Practice ? ( Extended Abstract )

It has been shown that quantifier-free bit-vector logic (QF BV) is NExpTime-complete, on account ... more It has been shown that quantifier-free bit-vector logic (QF BV) is NExpTime-complete, on account of the fact that the number of propositional variables in the SAT encoding of a QF BV formula grows exponentially with the length of the declarations of the bit-vector variables in the input formula. This level of complexity is surprising, given that in practice QF BV is being used successfully in a wide range of applications. This work points out that the high complexity does not necessary hold in practical applications of QF BV. We give two examples of easier families of QF BV problems. First, we demonstrate that, in a recent critical Intel application of QF BV in clock routing, the number of propositional variables grows polynomially with the length of the variable declarations, thus establishing that clock routing uses an NP-complete subset of QF BV. Second, we show that in another application, namely, microcode validation, register width should be viewed as a fixed parameter (more p...

Research paper thumbnail of On Optimizing a Generic Function in SAT

The goal of this study is to improve the scalability of today's SAT-based solutions for optim... more The goal of this study is to improve the scalability of today's SAT-based solutions for optimization problems and to pave the way towards extending the range of optimization problems solvable with SAT in practice. Let OptSAT be the problem of optimizing a generic Pseudo-Boolean function, given a satisfiable propositional formula F. We introduce an incremental and anytime incomplete algorithm for solving OptSAT, called Polosat. We show that integrating Polosat into a state-of-the-art open-source anytime MaxSAT solver significantly improves the solver's performance. Furthermore, we demonstrate that Polosat substantially improves the solution quality of an industrial placement tool, where placement is a sub-stage of the physical design stage of chip design.

Research paper thumbnail of From Total Assignment Enumeration to Modern SAT Solver

ArXiv, 2011

A new framework for presenting and analyzing the functionality of a modern DLL-based SAT solver i... more A new framework for presenting and analyzing the functionality of a modern DLL-based SAT solver is proposed. Our approach exploits the inherent relation between backtracking and resolution. We show how to derive the algorithm of a modern SAT solver from DLL step-by-step. We analyze the inference power of Boolean Constraint Propagation, Non-Chronological Backtracking and 1UIP-based Conflict-Directed Backjumping. Our work can serve as an introduction to a modern SAT solver functionality and as a basis for future work on the inference power of a modern SAT solver and on practical SAT solver design.

Research paper thumbnail of Routing under constraints

2016 Formal Methods in Computer-Aided Design (FMCAD), 2016

Research paper thumbnail of A Correct-by-Decision Solution for Simultaneous Place and Route

Computer Aided Verification, 2017

Research paper thumbnail of Bit-Vector Optimization

Tools and Algorithms for the Construction and Analysis of Systems, 2016

Research paper thumbnail of Local Search with a SAT Oracle for Combinatorial Optimization

NP-hard combinatorial optimization problems are pivotal in science and business. There exists a v... more NP-hard combinatorial optimization problems are pivotal in science and business. There exists a variety of approaches for solving such problems, but for problems with complex constraints and objective functions, local search algorithms scale the best. Such algorithms usually assume that finding a non-optimal solution with no other requirements is easy. However, what if it is NP-hard? In such case, a SAT solver can be used for finding the initial solution, but how can one continue solving the optimization problem? We offer a generic methodology, called Local Search with SAT Oracle (LSSO), to solve such problems. LSSO facilitates implementation of advanced local search methods, such as variable neighbourhood search, hill climbing and iterated local search, while using a SAT solver as an oracle. We have successfully applied our approach to solve a critical industrial problem of cell placement and productized our solution at Intel.

Research paper thumbnail of Chronological Backtracking

Theory and Applications of Satisfiability Testing – SAT 2018, 2018

Research paper thumbnail of Accelerated Deletion-based Extraction of Minimal Unsatisfiable Cores

Journal on Satisfiability, Boolean Modeling and Computation, 2014