Alfredo Olmos - Academia.edu (original) (raw)

Papers by Alfredo Olmos

Symposium on Integrated Circuits and Systems Design, Sep 8, 2003

The design of an IC on-chip oscillator including a temperature compensation circuitry, a robust s... more The design of an IC on-chip oscillator including a temperature compensation circuitry, a robust spread reduction technique and digital trimming is described. The IC oscillator provides a 12.8MHz clock signal with a frequency spread of ±25% before the 8-bits digital trimming. After centering the oscillator at the target frequency, a temperature compensated voltage and current reference circuit allows for less than ±5% frequency variation when operating from 3 to 5V of power supply and from-40 to 125°C of temperature range. The oscillator is implemented in a 0.5µm CMOS technology, occupies an area of 420x440µm 2 and dissipates less than 400µW at 3V of supply without requiring any external reference or components.

16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.

IEEE International Symposium on Circuits and Systems, 1998

We report the design of a chip-set containing several key components for an optical receiver in A... more We report the design of a chip-set containing several key components for an optical receiver in AlGaAs/GaAs HEMT technology. Different building blocks necessary to regenerate the signal coming from an optical data link have been characterized. The system provides a -3 dB bandwidth of 5 GHz with a transimpedance of 2.4 kΩ. Power consumption was estimated to be 350 mW

circuit random offset, component mismatching and process deviation

The design of a second-order continuous-time sigma-delta (ΣΔ) modulator working at a sampling rat... more The design of a second-order continuous-time sigma-delta (ΣΔ) modulator working at a sampling rate of 5 GHz and implemented on a 0.4 μm InGaP/InGaAs HEMT technology is described. A new polarity alternating feedback (PAF) technique is described and applied to the design of a high sampling frequency comparator. The fully differential architecture adopted for the modulator includes the PAF comparator

IEICE Transactions on Electronics, Mar 25, 1999

We fabricated and evaluated a second-order Σ∆ ADC with a polarity alternating feedback (PAF) comp... more We fabricated and evaluated a second-order Σ∆ ADC with a polarity alternating feedback (PAF) comparator based on 0.4μm InGaP/InGaAs enhancement and depletion mode high electron mobility transistors (E/D HEMT) technology. We propose a PAF technique for enhancing the sampling frequency and have applied the technique in the design of ADC circuit. The ADC has a signal-to-noise ratio (SNR) of 43 dB when operating at a differential clock frequency of 4.9 GHz, and has a power dissipation of 400 mW. key words: compound-semiconductor, HEMT, oversampling,

The design of the key components for a high sampling rate ΣΔ modulator implemented on a 0.4 μm In... more The design of the key components for a high sampling rate ΣΔ modulator implemented on a 0.4 μm InGaP-InGaAs HEMT technology is described. The circuit, a 2nd-order continuous-time ΣΔ modulator, has a fully differential architecture including pairs of highly linear V-I converters, high-speed opamps, high-speed 1-bit DAC units, and a new polarity alternating feedback (PAF) comparator. Working at a sampling

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Abstract This work presents a temperature compensation subsystem for a piezoresistive pressure mi... more Abstract This work presents a temperature compensation subsystem for a piezoresistive pressure microsensor system operating between 0-50 kPa for medical purposes. Different full scale span and offset voltage can be compensated easily against temperature effects ...

This paper presents a polarity alternating feedback (PAF) comparator with a high sampling speed i... more This paper presents a polarity alternating feedback (PAF) comparator with a high sampling speed in the range of two to six GS/s with a low power consumption of 140 mW including output bu#ers. Using the PAF comparator, we have designed and fabricated a secondorder ##ADC that has the lowest power consumption Manuscript received July 22, 1998.

Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th Anniversary of the MOSFET and 50th of the BJT. (Cat. No.98TH8350)

VLSI: Integrated Systems on Silicon, 1997

The design of a CMOS piezoresistive pressure sensor with mixed-signal circuitry to provide a digi... more The design of a CMOS piezoresistive pressure sensor with mixed-signal circuitry to provide a digital output is described. The on-chip sensor is a monolithic silicon etched diaphragm, built via post-processing, with the strain gauge composed of diffused resistors in an active Wheatstone bridge configuration. The amplifier's bridge is chopped for efficient low frequency noise and amplifier offset cancellations. The A-to-D converter is based on a second-order Al: modulator including 6 bits DAC units for sensor offset calibration. The circuit has temperature compensation of both full output scale and offset. Overall system resolution is 12 bits, corresponding to 72dB dynamic range, while the pressure range is 0 to 50kPa. Pulsed mode operation allows for low power dissipation (<lmW) at 3V supply voltage. This device is intended to be used in biomedical applications such as non-invasive blood pressure measurement and diagnostics.

2014 IEEE International Conference on RFID (IEEE RFID), 2014

ABSTRACT This paper presents a low power, low voltage RF/analog front-end architecture for LF RFI... more ABSTRACT This paper presents a low power, low voltage RF/analog front-end architecture for LF RFID tags with a dynamic power sensing scheme. The front-end converts the incoming RF power into DC using a system that adjusts its performance according to the available RF power. The power sensing scheme, composed by a feedback system that &quot;regulates&quot; the RF clamp stage, improves the incoming available power to the system. All building blocks together with the RF air link and antenna interface were modeled using digital and electrical signals with high abstraction level, validating the architecture. Part of the proposed AFE architecture was silicon proven in a preliminary CMOS 0.18μm process test chip. This preliminary part includes the regulation stages and part of the RF section. It shows excellent results for a maximum of 3μA DC current consumption, over a wide range of input RF power.

Abstract - This paper describes the design of a 12-bit fully differential Switched-Capacitor (SC)... more Abstract - This paper describes the design of a 12-bit fully differential Switched-Capacitor (SC) Programmable Gain Amplifier (PGA) optimized for motor control application and implemented using Correlated Double Sampling (CDS) technique. The PGA performs differential to ...

ABSTRACT Nowadays some microcontroller clock circuits have been implemented using relaxation osci... more ABSTRACT Nowadays some microcontroller clock circuits have been implemented using relaxation oscillators instead of quartz type approach to attend cost effective designs. The oscillator is compensated over temperature and power supply and trimming during device test phase adjusts the oscillation frequency on target to overcome process variations. In that way, the relaxation oscillator becomes competitive with regard to ceramic resonator options. However, robust applications as industrial, automotive and aero spatial, requires aggressive EMC tests reproducing the behavior in these environments. High levels of RF interference introduce frequency deviation, jitter or clock corruption causing severe faults on the application. This work discusses the impact of RF interference in relaxation oscillators proposing a strategy to implement test mode in microcontrollers and other complex SOCs, allowing yet characterization and fault debug. Theoretical analysis and experimental results with a silicon implementation are presented and discussed.

Crystal oscillators are usually implemented using Pierces configuration due to its high stability... more Crystal oscillators are usually implemented using Pierces configuration due to its high stability, small amount of components, and easy adjustment. With technology development and device shrinking, modern microcontroller embedded oscillators include all network components integrated on chip to attend cost-effective designs supporting both crystals and ceramic resonators. This fact makes the oscillator more sensitive to feedback network load and strays

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

The design of a temperature compensated IC on-chip oscillator and a low voltage detection circuit... more The design of a temperature compensated IC on-chip oscillator and a low voltage detection circuitry sharing the bandgap reference is described. The circuit includes a new bandgap isolation strategy to reduce oscillator noise coupled through the current sources. The IC oscillator provides a selectable clock (11.6 MHz or 21.4 MHz) with digital trimming to minimize process variations. After fine-tuning the