Andy Tseng - Academia.edu (original) (raw)

Papers by Andy Tseng

3rd Electronics System Integration Technology Conference ESTC, 2010

Page 1. Fine Pitch Copper Wire Bonding Introduction to High Volume Production Bernd K. Appelt, An... more Page 1. Fine Pitch Copper Wire Bonding Introduction to High Volume Production Bernd K. Appelt, Andy Tseng, Yi-Shao Lai* ASE Group Inc. ... 10Year Gold 1400 1200 1000 c g 800 " 8. 600 ill ::::I 400 200 High 1214.80 Loy 25'5.30 1400 ...

2012 2nd IEEE CPMT Symposium Japan, 2012

Over the course of the last five years, fine pitch Cu wire bonding has gained a very large market... more Over the course of the last five years, fine pitch Cu wire bonding has gained a very large market share in the wire bond packaging market driven primarily by very high Au commodity prices. Virtually all IDMs and OSATs do offer Cu wire bond products. In ASE the penetration rate is reaching 60% or more than 9.5 billion units in shipment to date. The reliability has reached levels which equate to more than 6X of typical JEDEC package reliability testing protocols, and now, automotive as well as networking customers are ready to accept Cu wire bonded products for their applications. Current shipments do include 40 and 45 nm wafer technology and the question is arising how far can Cu wire bonding go? The ASE Cu wire bonding roadmap will be presented which aims at sustaining wire bonding in Cu to at least the 20 nm node. Qualification data will be presented for the 28 nm node based on collaboration with wafer fabs. Customer die qualifications are in progress.

2011 IEEE 13th Electronics Packaging Technology Conference, 2011

Wire bonding has been the predominant interconnect technology for more than 40 years and even tod... more Wire bonding has been the predominant interconnect technology for more than 40 years and even today is holding a market share of more than 85%. The standard wire material has been gold albeit copper and aluminum wires have been used for 20 or so years in power applications. In the past few years, economics, i.e. the explosive increase in gold commodity pricing, have lead to a rapid conversion of fine diameter gold wire packages to copper wire packages. The conversion was lead by consumer products which were most price sensitive and perceived to be least demanding in reliability due to the nature of the application and the relatively short life. For these products, a good track record has been established which then lead to an extension of the applications to computer and communication applications. Now, automotive and networking applications are also implementing copper wires as interconnects without sacrificing their stringent reliability and long life requirements. All of the recent conversion activity has spurned many research and application publications about copper wire bonding Discussion 1 Section Header to report on copper wire itself, the bonding process and intermetallic compound formation, effect of mold compounds, reliability performance, etc. Wire suppliers have developed and introduced new copper based wires, mold compound suppliers have purified mold compounds to suppress corrosion and equipment suppliers have developed copper wire specific bonders. Here, the successful implementation and ‘long term’ copper wire bonding experience for a wide range of applications and range of wafer nodes will be reported. A strict methodology for assessing bondability for any new device will be discussed. This methodology was found to be necessary due to the subtle differences in pad design even when devices are built in the same fab. Clearly, advanced wafer nodes based on LK and ELK dielectrics have rather small process windows and do require rigorous tuning of bonders control of assembly processes and manufacturing floor as well as specific training of operators. Such a methodology plus the proper choice of materials are essential for the success and the long term reliability of copper wire bonds as will be demonstrated in this paper. It will be shown that JEDEC tests can be extended to exceed the typical test durations by more than five or six times. The high reliability of copper wire bonds is based on the very slow copper aluminum intermetallic growth. Such reliability performance as well as near gold assembly yields lead to the level of confidence to start automotive application qualifications. The first set of results of successful automotive application qualification per ACE-Q100 requirements will be presented to demonstrate readiness for manufacturing.

2010 12th Electronics Packaging Technology Conference, 2010

Wire bonding has been the dominant mode of chip to substrate interconnection for many decades. Th... more Wire bonding has been the dominant mode of chip to substrate interconnection for many decades. The most common metal used has been gold which is rather malleable and very resistant to oxidation and corrosion. The surge in commodity prices over the last few years has prompted the introduction of copper as a lower cost alternative. While copper has some advantages

2012 2nd IEEE CPMT Symposium Japan, 2012

The drive for miniaturization of electronic packaging is continuing relentlessly due to ever more... more The drive for miniaturization of electronic packaging is continuing relentlessly due to ever more functionality in smaller, lighter mobile products. Consequently, innovations are required in packaging technology, and more importantly, in enabled volume manufacturing. Some recent trends in thin products and packaging will be high-lighted and compared to the JEDEC standards for packages. The ASE roadmaps for package size reductions will be presented with particular focus on prepreg based substrate technology. A single sided substrate has been developed and is currently shipping in high volume. The manufacturing concept for this substrate has been adapted to build coreless substrates based on prepreg which are currently in characterization. Further adaptation has led to embedded component, actives and passives, substrates which are currently in qualification. For the later, a new manufacturing form factor has been chosen to take advantage of the assembly infrastructure and to maximize the yield of the substrate which is a key factor for the commercial success of this technology. ASE is offering these substrates in full turnkey service from wafer sort to bumping to embedding in the substrate to assembly of top components, balling and final test.

2012 14th International Conference on Electronic Materials and Packaging (EMAP), 2012

The booming business of mobile applications like cell phones, tablet computers, etc., is intimate... more The booming business of mobile applications like cell phones, tablet computers, etc., is intimately linked to their thin packaging format and is continuing the drive for ever thinner applications. Concomitantly, the electronic packages inside the applications need to shrink i.e. dice, substrates, interconnects and assembly all need to contribute to the shrinkage. A packaging roadmap will be presented that aligns with this industry trend and examples of package types satisfying the roadmap will be presented. For two specific package types, aQFN and a-S3 BGA, more details will be provided for the package cross-section as well as the manufacturing process flow on a substrate and assembly level. Package and board level reliability has been collected to demonstrate the viability of these packages which have already reached the high volume manufacturing stage.

Microelectronics Reliability, 2011

Wire bonding is the predominant mode of interconnection in electronic packaging. Gold wire bondin... more Wire bonding is the predominant mode of interconnection in electronic packaging. Gold wire bonding has been refined again and again to retain control of interconnect technology due to its ease of workability and years of reliability data. Economic realities are now enabling fine diameter copper wire to compete with gold wire. It needs to be demonstrated however that known challenges in the assembly process and long term reliability can be managed successfully. Here, a rigorous methodology has been established to introduce copper wire bonding on new as well as converted dice into manufacturing. Manufacturing efficiencies and yields have been driven to be equivalent to gold wires. Reliability testing has passed the usual criteria and has been extended to demonstrate the viability of this technology. Interfacial analysis has confirmed the observations that intermetallic compounds form and grow slowly.

2009 International Conference on Electronic Packaging Technology & High Density Packaging, 2009

... Die size 17×18 mm is bonded on 37.5×37.5mm HFCBGA. Figure 6 Flip Chip assembly process flow. ... more ... Die size 17×18 mm is bonded on 37.5×37.5mm HFCBGA. Figure 6 Flip Chip assembly process flow. Table 6 Reliability test result of twelve underfills ... Figure 8 R1/R2 passed TCB 200, 400, 600, 800 and 1000 cycles. Figure 9 R3 Underfill crack and tiny delam after TCB 600. ...

3rd Electronics System Integration Technology Conference ESTC, 2010

Page 1. Fine Pitch Copper Wire Bonding Introduction to High Volume Production Bernd K. Appelt, An... more Page 1. Fine Pitch Copper Wire Bonding Introduction to High Volume Production Bernd K. Appelt, Andy Tseng, Yi-Shao Lai* ASE Group Inc. ... 10Year Gold 1400 1200 1000 c g 800 " 8. 600 ill ::::I 400 200 High 1214.80 Loy 25'5.30 1400 ...

2012 2nd IEEE CPMT Symposium Japan, 2012

Over the course of the last five years, fine pitch Cu wire bonding has gained a very large market... more Over the course of the last five years, fine pitch Cu wire bonding has gained a very large market share in the wire bond packaging market driven primarily by very high Au commodity prices. Virtually all IDMs and OSATs do offer Cu wire bond products. In ASE the penetration rate is reaching 60% or more than 9.5 billion units in shipment to date. The reliability has reached levels which equate to more than 6X of typical JEDEC package reliability testing protocols, and now, automotive as well as networking customers are ready to accept Cu wire bonded products for their applications. Current shipments do include 40 and 45 nm wafer technology and the question is arising how far can Cu wire bonding go? The ASE Cu wire bonding roadmap will be presented which aims at sustaining wire bonding in Cu to at least the 20 nm node. Qualification data will be presented for the 28 nm node based on collaboration with wafer fabs. Customer die qualifications are in progress.

2011 IEEE 13th Electronics Packaging Technology Conference, 2011

Wire bonding has been the predominant interconnect technology for more than 40 years and even tod... more Wire bonding has been the predominant interconnect technology for more than 40 years and even today is holding a market share of more than 85%. The standard wire material has been gold albeit copper and aluminum wires have been used for 20 or so years in power applications. In the past few years, economics, i.e. the explosive increase in gold commodity pricing, have lead to a rapid conversion of fine diameter gold wire packages to copper wire packages. The conversion was lead by consumer products which were most price sensitive and perceived to be least demanding in reliability due to the nature of the application and the relatively short life. For these products, a good track record has been established which then lead to an extension of the applications to computer and communication applications. Now, automotive and networking applications are also implementing copper wires as interconnects without sacrificing their stringent reliability and long life requirements. All of the recent conversion activity has spurned many research and application publications about copper wire bonding Discussion 1 Section Header to report on copper wire itself, the bonding process and intermetallic compound formation, effect of mold compounds, reliability performance, etc. Wire suppliers have developed and introduced new copper based wires, mold compound suppliers have purified mold compounds to suppress corrosion and equipment suppliers have developed copper wire specific bonders. Here, the successful implementation and ‘long term’ copper wire bonding experience for a wide range of applications and range of wafer nodes will be reported. A strict methodology for assessing bondability for any new device will be discussed. This methodology was found to be necessary due to the subtle differences in pad design even when devices are built in the same fab. Clearly, advanced wafer nodes based on LK and ELK dielectrics have rather small process windows and do require rigorous tuning of bonders control of assembly processes and manufacturing floor as well as specific training of operators. Such a methodology plus the proper choice of materials are essential for the success and the long term reliability of copper wire bonds as will be demonstrated in this paper. It will be shown that JEDEC tests can be extended to exceed the typical test durations by more than five or six times. The high reliability of copper wire bonds is based on the very slow copper aluminum intermetallic growth. Such reliability performance as well as near gold assembly yields lead to the level of confidence to start automotive application qualifications. The first set of results of successful automotive application qualification per ACE-Q100 requirements will be presented to demonstrate readiness for manufacturing.

2010 12th Electronics Packaging Technology Conference, 2010

Wire bonding has been the dominant mode of chip to substrate interconnection for many decades. Th... more Wire bonding has been the dominant mode of chip to substrate interconnection for many decades. The most common metal used has been gold which is rather malleable and very resistant to oxidation and corrosion. The surge in commodity prices over the last few years has prompted the introduction of copper as a lower cost alternative. While copper has some advantages

2012 2nd IEEE CPMT Symposium Japan, 2012

The drive for miniaturization of electronic packaging is continuing relentlessly due to ever more... more The drive for miniaturization of electronic packaging is continuing relentlessly due to ever more functionality in smaller, lighter mobile products. Consequently, innovations are required in packaging technology, and more importantly, in enabled volume manufacturing. Some recent trends in thin products and packaging will be high-lighted and compared to the JEDEC standards for packages. The ASE roadmaps for package size reductions will be presented with particular focus on prepreg based substrate technology. A single sided substrate has been developed and is currently shipping in high volume. The manufacturing concept for this substrate has been adapted to build coreless substrates based on prepreg which are currently in characterization. Further adaptation has led to embedded component, actives and passives, substrates which are currently in qualification. For the later, a new manufacturing form factor has been chosen to take advantage of the assembly infrastructure and to maximize the yield of the substrate which is a key factor for the commercial success of this technology. ASE is offering these substrates in full turnkey service from wafer sort to bumping to embedding in the substrate to assembly of top components, balling and final test.

2012 14th International Conference on Electronic Materials and Packaging (EMAP), 2012

The booming business of mobile applications like cell phones, tablet computers, etc., is intimate... more The booming business of mobile applications like cell phones, tablet computers, etc., is intimately linked to their thin packaging format and is continuing the drive for ever thinner applications. Concomitantly, the electronic packages inside the applications need to shrink i.e. dice, substrates, interconnects and assembly all need to contribute to the shrinkage. A packaging roadmap will be presented that aligns with this industry trend and examples of package types satisfying the roadmap will be presented. For two specific package types, aQFN and a-S3 BGA, more details will be provided for the package cross-section as well as the manufacturing process flow on a substrate and assembly level. Package and board level reliability has been collected to demonstrate the viability of these packages which have already reached the high volume manufacturing stage.

Microelectronics Reliability, 2011

Wire bonding is the predominant mode of interconnection in electronic packaging. Gold wire bondin... more Wire bonding is the predominant mode of interconnection in electronic packaging. Gold wire bonding has been refined again and again to retain control of interconnect technology due to its ease of workability and years of reliability data. Economic realities are now enabling fine diameter copper wire to compete with gold wire. It needs to be demonstrated however that known challenges in the assembly process and long term reliability can be managed successfully. Here, a rigorous methodology has been established to introduce copper wire bonding on new as well as converted dice into manufacturing. Manufacturing efficiencies and yields have been driven to be equivalent to gold wires. Reliability testing has passed the usual criteria and has been extended to demonstrate the viability of this technology. Interfacial analysis has confirmed the observations that intermetallic compounds form and grow slowly.

2009 International Conference on Electronic Packaging Technology & High Density Packaging, 2009

... Die size 17×18 mm is bonded on 37.5×37.5mm HFCBGA. Figure 6 Flip Chip assembly process flow. ... more ... Die size 17×18 mm is bonded on 37.5×37.5mm HFCBGA. Figure 6 Flip Chip assembly process flow. Table 6 Reliability test result of twelve underfills ... Figure 8 R1/R2 passed TCB 200, 400, 600, 800 and 1000 cycles. Figure 9 R3 Underfill crack and tiny delam after TCB 600. ...