Antonio Liscidini - Academia.edu (original) (raw)

Papers by Antonio Liscidini

IEEE Open Journal of the Solid-State Circuits Society

A power-scalable RF front-end using quantized analog signal processing is presented. The front-en... more A power-scalable RF front-end using quantized analog signal processing is presented. The front-end is based on a voltage-mode power-scalable approach which allows the power dissipation to be scaled upon the operative scenario and to perform an agile calibration for mismatch impairments. Power and input dynamic range can be scaled upon the desired 1-dB compression point (1dBCP) (from −15.3 to 0.5 dBm) while keeping the same sensitivity with 2.5-dB NF. Signal path power can vary between 3.3 and 6.4 mW while clock generation and distribution power can vary between 1.6 and 18.5 mW/GHz, with a phase noise as low as −171.2 dBc/Hz. After calibration, IM2 and IM3 improved up to 33 dB while 1dBCP improved by 1 dB, which resulted in achieving an IIP3 of 26.1 dBm and IIP2 of 71 dBm at 0-dBm 1dBCP. INDEX TERMS Digital calibration, dynamic range (DR), high linearity, low power, nonuniform quantization, power scalable, quantized analog (QA), surface acoustic wave (SAW)-less, voltage-mode. I. INTRODUCTION T HE REMOVAL of surface acoustic wave (SAW) filters on the modern RF front-end has become a popular trend to reduce the overall cost and save precious realestate on the device [1], [2], [3], [4], [5], [6]. However, lack of high-Q filters demands high dynamic range (DR) from the RF front-end as well as requiring low noise floor even when large blockers are present (which generally is the case for SAW-less receivers). Large power consumption in both signal and local oscillator (LO) paths are needed to meet these stringent requirements. In modern RF front-ends, the gain in the signal path is limited by using the current-mode approach to increase input 1-dB compression point (1dBCP). This solution however requires a transimpedance amplifier (TIA) in the baseband, whose power can grow significantly when low input-referred noise and high compression point are demanded. In the LO path, the phase noise (PN) must be limited to reduce the impact of reciprocal mixing when large blockers are present. This can only be achieved by increasing the clock buffer sizes and consume significantly more power (e.g., 33 mW/GHz to get a PN as low as −170 dBc/Hz [7]). A. STATE-OF-THE-ART SAW-LESS RF RECEIVERS REVIEW Voltage-mode circuits have been widely implemented in RF front-end in the past. However, after the introduction of current passive mixers, which are technology-scaling friendly and are more compatible with modern low-voltage supplies [8], current-mode approaches have become the de-facto standard, especially in SAW-less applications. As mentioned previously, one of the major advantages of using the currentmode approach is minimization of the output swing which, in turn, increases the upper limit of the DR. Nevertheless, current-mode front-ends need power hungry TIAs with stringent noise requirements due to the inherent lack of RF gain in front of them. Fig. 2 provides state-of-the-art RF receivers as well as an overview of their performance and power dissipation breakdown (power consumption is reported for a common operative carrier at 2 GHz). While the majority of

IEEE Open Journal of Circuits and Systems, 2022

This work was supported in part by Analog Devices Canada and in part by the Natural Sciences and ... more This work was supported in part by Analog Devices Canada and in part by the Natural Sciences and Engineering Research Council (NSERC) of Canada.

IEEE Solid-State Circuits Magazine, 2014

This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this... more This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this periodical during 2014, and items from previous years that were commented upon or corrected in 2014. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017

An overview and comparison is provided of the different emerging wireless standards and their cir... more An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.

A unified description of multiple feedback common- gate low-noise amplifiers (LNAs) is presented,... more A unified description of multiple feedback common- gate low-noise amplifiers (LNAs) is presented, providing analyt- ical expressions for gain, noise figure, linearity, and stability con- ditions. Moreover, from the theory, a new methodology for LNA optimization is developed. This new approach, called adaptive op- timization, uses the ability to reconfigure the feedback network to match the amplifier characteristics to the changing working condi- tions. Results of simulation of LNAs with different feedback types are shown, and they confirm the theory presented. Index Terms—Common gate, feedback amplifier, high linearity, low-noise amplifier (LNA), multiband, multistandard, negative feedback, positive feedback, reconfigurability.

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018

This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power applica... more This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power application. By exploiting transistors' class-AB operation in both the RF and baseband sections, the receiver front-end achieves a very low sensitivity and an elevated blocker tolerance while keeping a low power consumption. Such performance makes the receiver suitable for both short-range (e.g. 802.15.4) and long-range (e.g. LoRa) applications. The proposed RF front-end has been implemented in 0.13um CMOS technology, operates in the 868/915MHz ISM bands, and exhibits an in-band gain of 50dB, noise figure of 2.7dB, out-of-band HP3 of +2dBm, out-of-band IIP2 of +37dBm, out-of-band P1dB of −10.5dBm, while draining 2.1mA from a 1.2 V supply.

IEEE Open Journal of the Solid-State Circuits Society, 2021

IEEE Journal of Solid-State Circuits, 2021

An injection locking power amplifier is presented. The proposed solution, tailored to quadrature ... more An injection locking power amplifier is presented. The proposed solution, tailored to quadrature phase shift keying (QPSK) modulation for IoT has been realized by exploiting the property of an injection-locked frequency divider to work as a phase rotator. Hence, the divider’s output is directly coupled to the antenna by a transformer to deliver the desired output power. The combination of these two ideas resulted in a high-efficiency, high-bandwidth QPSK RF front-end for IoT, capable of operating at up to 120 Mbit/s and delivering 1.3-mW output power while burning 3.4 mW.

IEEE Transactions on Biomedical Circuits and Systems, 2017

Electronics Letters, 2016

The impact of thermal noise in voltage- and time-domain analogue signal processing is discussed. ... more The impact of thermal noise in voltage- and time-domain analogue signal processing is discussed. Despite the technology scaling allows to resolve smaller time differences, it will be shown that in CMOS technologies voltage signal processing have a better fundamental limit compared with its time counterpart.

IEEE Custom Integrated Circuits Conference 2006, 2006

A new topology of transformer based low noise amplifier is presented. The structure realizes a lo... more A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013

ABSTRACT This Forum explores the primary challenges in the generation and distribution of frequen... more ABSTRACT This Forum explores the primary challenges in the generation and distribution of frequency-reference signals in modern integrated circuits (analog and digital). Based on a bottom-up approach, the Forum begins with an overview of the building blocks used for frequency generation and distribution. It continues by discussing particular challenges presented by the design of frequency synthesizers and their interaction with the rest of the system. The first three talks provide insights into the design of frequency generators: harmonic oscillators, ring oscillators, and MEMS topologies. The fourth presentation deals with various single-and dual-modulus divider topologies necessary for wireless or wireline applications. Then, frequency synthesizers for millimeter-wave wireless communications and PLLs for wireline applications are presented. The last two talks give an overview of the main challenges in clock distribution for both microprocessors and RF analog transceivers. The Forum concludes with a brief panel discussion, providing an opportunity for participants to give feedback and ask questions.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2008

A unified description of multiple feedback commongate low-noise amplifiers (LNAs) is presented, p... more A unified description of multiple feedback commongate low-noise amplifiers (LNAs) is presented, providing analytical expressions for gain, noise figure, linearity, and stability conditions. Moreover, from the theory, a new methodology for LNA optimization is developed. This new approach, called adaptive optimization, uses the ability to reconfigure the feedback network to match the amplifier characteristics to the changing working conditions. Results of simulation of LNAs with different feedback types are shown, and they confirm the theory presented.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2012

A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is present... more A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications-Universal Mobile Telecommunications System (GSM-UMTS) reconfigurable receiver.

IEEE Journal of Solid-State Circuits, 2014

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintai... more A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switchpair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the singleswitch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of 129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of 134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of 185 dBc/Hz.

IEEE Journal of Solid-State Circuits, 2014

ABSTRACT An intuitive yet sufficiently accurate formulation of the phase noise of various commonl... more ABSTRACT An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the actual one is derived for all topologies considered. Measurements on a dedicated chip prototype that integrates two high performance topologies allow to verify, in an unbiased way, the accuracy of the predictions. A very good agreement between the model and both simulation and measurement is obtained.

IEEE Journal of Solid-State Circuits, 2013

IEEE Open Journal of the Solid-State Circuits Society

A power-scalable RF front-end using quantized analog signal processing is presented. The front-en... more A power-scalable RF front-end using quantized analog signal processing is presented. The front-end is based on a voltage-mode power-scalable approach which allows the power dissipation to be scaled upon the operative scenario and to perform an agile calibration for mismatch impairments. Power and input dynamic range can be scaled upon the desired 1-dB compression point (1dBCP) (from −15.3 to 0.5 dBm) while keeping the same sensitivity with 2.5-dB NF. Signal path power can vary between 3.3 and 6.4 mW while clock generation and distribution power can vary between 1.6 and 18.5 mW/GHz, with a phase noise as low as −171.2 dBc/Hz. After calibration, IM2 and IM3 improved up to 33 dB while 1dBCP improved by 1 dB, which resulted in achieving an IIP3 of 26.1 dBm and IIP2 of 71 dBm at 0-dBm 1dBCP. INDEX TERMS Digital calibration, dynamic range (DR), high linearity, low power, nonuniform quantization, power scalable, quantized analog (QA), surface acoustic wave (SAW)-less, voltage-mode. I. INTRODUCTION T HE REMOVAL of surface acoustic wave (SAW) filters on the modern RF front-end has become a popular trend to reduce the overall cost and save precious realestate on the device [1], [2], [3], [4], [5], [6]. However, lack of high-Q filters demands high dynamic range (DR) from the RF front-end as well as requiring low noise floor even when large blockers are present (which generally is the case for SAW-less receivers). Large power consumption in both signal and local oscillator (LO) paths are needed to meet these stringent requirements. In modern RF front-ends, the gain in the signal path is limited by using the current-mode approach to increase input 1-dB compression point (1dBCP). This solution however requires a transimpedance amplifier (TIA) in the baseband, whose power can grow significantly when low input-referred noise and high compression point are demanded. In the LO path, the phase noise (PN) must be limited to reduce the impact of reciprocal mixing when large blockers are present. This can only be achieved by increasing the clock buffer sizes and consume significantly more power (e.g., 33 mW/GHz to get a PN as low as −170 dBc/Hz [7]). A. STATE-OF-THE-ART SAW-LESS RF RECEIVERS REVIEW Voltage-mode circuits have been widely implemented in RF front-end in the past. However, after the introduction of current passive mixers, which are technology-scaling friendly and are more compatible with modern low-voltage supplies [8], current-mode approaches have become the de-facto standard, especially in SAW-less applications. As mentioned previously, one of the major advantages of using the currentmode approach is minimization of the output swing which, in turn, increases the upper limit of the DR. Nevertheless, current-mode front-ends need power hungry TIAs with stringent noise requirements due to the inherent lack of RF gain in front of them. Fig. 2 provides state-of-the-art RF receivers as well as an overview of their performance and power dissipation breakdown (power consumption is reported for a common operative carrier at 2 GHz). While the majority of

IEEE Open Journal of Circuits and Systems, 2022

This work was supported in part by Analog Devices Canada and in part by the Natural Sciences and ... more This work was supported in part by Analog Devices Canada and in part by the Natural Sciences and Engineering Research Council (NSERC) of Canada.

IEEE Solid-State Circuits Magazine, 2014

This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this... more This index covers all technical items-papers, correspondence, reviews, etc.-that appeared in this periodical during 2014, and items from previous years that were commented upon or corrected in 2014. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017

An overview and comparison is provided of the different emerging wireless standards and their cir... more An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.

A unified description of multiple feedback common- gate low-noise amplifiers (LNAs) is presented,... more A unified description of multiple feedback common- gate low-noise amplifiers (LNAs) is presented, providing analyt- ical expressions for gain, noise figure, linearity, and stability con- ditions. Moreover, from the theory, a new methodology for LNA optimization is developed. This new approach, called adaptive op- timization, uses the ability to reconfigure the feedback network to match the amplifier characteristics to the changing working condi- tions. Results of simulation of LNAs with different feedback types are shown, and they confirm the theory presented. Index Terms—Common gate, feedback amplifier, high linearity, low-noise amplifier (LNA), multiband, multistandard, negative feedback, positive feedback, reconfigurability.

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018

This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power applica... more This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power application. By exploiting transistors' class-AB operation in both the RF and baseband sections, the receiver front-end achieves a very low sensitivity and an elevated blocker tolerance while keeping a low power consumption. Such performance makes the receiver suitable for both short-range (e.g. 802.15.4) and long-range (e.g. LoRa) applications. The proposed RF front-end has been implemented in 0.13um CMOS technology, operates in the 868/915MHz ISM bands, and exhibits an in-band gain of 50dB, noise figure of 2.7dB, out-of-band HP3 of +2dBm, out-of-band IIP2 of +37dBm, out-of-band P1dB of −10.5dBm, while draining 2.1mA from a 1.2 V supply.

IEEE Open Journal of the Solid-State Circuits Society, 2021

IEEE Journal of Solid-State Circuits, 2021

An injection locking power amplifier is presented. The proposed solution, tailored to quadrature ... more An injection locking power amplifier is presented. The proposed solution, tailored to quadrature phase shift keying (QPSK) modulation for IoT has been realized by exploiting the property of an injection-locked frequency divider to work as a phase rotator. Hence, the divider’s output is directly coupled to the antenna by a transformer to deliver the desired output power. The combination of these two ideas resulted in a high-efficiency, high-bandwidth QPSK RF front-end for IoT, capable of operating at up to 120 Mbit/s and delivering 1.3-mW output power while burning 3.4 mW.

IEEE Transactions on Biomedical Circuits and Systems, 2017

Electronics Letters, 2016

The impact of thermal noise in voltage- and time-domain analogue signal processing is discussed. ... more The impact of thermal noise in voltage- and time-domain analogue signal processing is discussed. Despite the technology scaling allows to resolve smaller time differences, it will be shown that in CMOS technologies voltage signal processing have a better fundamental limit compared with its time counterpart.

IEEE Custom Integrated Circuits Conference 2006, 2006

A new topology of transformer based low noise amplifier is presented. The structure realizes a lo... more A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013

ABSTRACT This Forum explores the primary challenges in the generation and distribution of frequen... more ABSTRACT This Forum explores the primary challenges in the generation and distribution of frequency-reference signals in modern integrated circuits (analog and digital). Based on a bottom-up approach, the Forum begins with an overview of the building blocks used for frequency generation and distribution. It continues by discussing particular challenges presented by the design of frequency synthesizers and their interaction with the rest of the system. The first three talks provide insights into the design of frequency generators: harmonic oscillators, ring oscillators, and MEMS topologies. The fourth presentation deals with various single-and dual-modulus divider topologies necessary for wireless or wireline applications. Then, frequency synthesizers for millimeter-wave wireless communications and PLLs for wireline applications are presented. The last two talks give an overview of the main challenges in clock distribution for both microprocessors and RF analog transceivers. The Forum concludes with a brief panel discussion, providing an opportunity for participants to give feedback and ask questions.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2008

A unified description of multiple feedback commongate low-noise amplifiers (LNAs) is presented, p... more A unified description of multiple feedback commongate low-noise amplifiers (LNAs) is presented, providing analytical expressions for gain, noise figure, linearity, and stability conditions. Moreover, from the theory, a new methodology for LNA optimization is developed. This new approach, called adaptive optimization, uses the ability to reconfigure the feedback network to match the amplifier characteristics to the changing working conditions. Results of simulation of LNAs with different feedback types are shown, and they confirm the theory presented.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2012

A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is present... more A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications-Universal Mobile Telecommunications System (GSM-UMTS) reconfigurable receiver.

IEEE Journal of Solid-State Circuits, 2014

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintai... more A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switchpair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the singleswitch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of 129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of 134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of 185 dBc/Hz.

IEEE Journal of Solid-State Circuits, 2014

ABSTRACT An intuitive yet sufficiently accurate formulation of the phase noise of various commonl... more ABSTRACT An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the actual one is derived for all topologies considered. Measurements on a dedicated chip prototype that integrates two high performance topologies allow to verify, in an unbiased way, the accuracy of the predictions. A very good agreement between the model and both simulation and measurement is obtained.

IEEE Journal of Solid-State Circuits, 2013