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Papers by Arthur van Roermund

Communications Engineer, 2003

DVB-T is a transmission standard that enables good reception even when the transmission channel i... more DVB-T is a transmission standard that enables good reception even when the transmission channel is subject to frequency-selective fading. When DVB-T is used for a mobile microwave link, flat fading can occasionally occur. In this article, a time interleaving layer is proposed that makes the transmission more rugged under flat fading conditions. The proposed mechanism involves an additional Reed-Solomon coding step and a modified data transmission order, and preserves the DVB-T layer of the communications channel. This document was originally published in IEE Communications Engineer (June/July 2003).

Wide-Bandwidth High-Dynamic Range D/A Converters

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011

This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM... more This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM band and implemented in 45nm CMOS technology. The PA is based on a distributed active transformer (DAT) topology which enables simultaneous power combining and realization of an efficient impedance matching. To cope with the asymmetric nature of DAT, resulting in common-mode and unequal differential voltage-swings at its input-ports, this paper presents two universal methods which do not impose any layout restrictions and layout adjustments. The realized PA achieves 13.2dBm output power at 1dB compression, a saturated output power of 16.3dBm, a PAE of 8.7% and 18.7dBm OIP3, while consuming 178mA at 1.8V.

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

This paper presents a new on-chip low-power selfcalibration apparatus implemented in a 12-bit cur... more This paper presents a new on-chip low-power selfcalibration apparatus implemented in a 12-bit currentsteering 250nm CMOS DAC. The DAC core consists of a non-calibrated binary LSB part and a calibrated thermometer MSB part. The thermometer currents are generated by combining a coarse 10-bit accurate current with a fine calibrating current provided by a small calibrating DAC (CALDAC). The magnitude of the fine current is determined in the digital domain and optimized for overall post-calibration accuracy. This digital process acquires mismatch error information from on an on-chip single bit ADC. The whole calibration process is executed once at chip power-up and the calibration results are recorded. During the normal operation of the DAC, no active calibration operations are present and the fine currents are kept static, so that the advantages of calibration are maintained even at very high conversion rates. The self-calibrated DAC achieves 12-bit static and dynamic linearity, while occupying smaller silicon area due to the intrinsic 10-bit accuracy of the DAC core.

2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), 2016

This paper presents a LED driver based on a new Hybrid-Switched Capacitor Converter (H-SCC) opera... more This paper presents a LED driver based on a new Hybrid-Switched Capacitor Converter (H-SCC) operating in the MHz range, which uses the internal pulsed nodes of a Dickson converter and an LC output network to provide output current dimming. The converter is implemented using 5V integrated capacitors and switches in a 0.18μm bulk CMOS technology. The experimental results show that the proposed LED driver has a power density of 122mW/mm2 and an efficiency of 79%, and only needs a small 40nH inductor.

IEEE MTT-S International Microwave Symposium Digest, 2003, 2003

In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varyin... more In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varying the phase shift of the circuits that couple two LC oscillator stages, a 1.1 GHz: tuning range is achieved. Dependency of tuning range and phase noise on the quality factor of the LC resonators is explored on the behavioral level. Expressions are given for the tuning range and an effective quality factor, as a function of the resonator quality, its phase shift and its resonance frequency. The oscillator is realized in a mainstream 30 GHz f/sub T/ BiCMOS process and dissipates 45 mW (nominal) with 2.7 V supply voltage. The dependency of the tuning range on the resonator quality is measured by varying the quality factor of a varactor incorporated in the LC resonators of the I/Q oscillator. Measured /spl Lscr/(2 MHz) is -108 dBc/Hz at 5.6 GHz.

Wide-Bandwidth High-Dynamic Range D/A Converters

A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB r... more A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.

80th ARFTG Microwave Measurement Conference, 2012

This paper describes a novel broadband hybrid load-and source-pull system. It eliminates the need... more This paper describes a novel broadband hybrid load-and source-pull system. It eliminates the need for a variable attenuator and variable phase-shifter and it employs the conventional passive tuner calibration procedure. It is established around a Gamma Boosting Unit (GBU), which is composed of two directional couplers and an auxiliary amplifier and which resembles a positive feedback loop. Device measurements at 900MHz and 30GHz demonstrate a significant improvement for the measured output efficiency and transducer gain.

9th International Conference on Electronics, Circuits and Systems

In this paper, the analysis of a multi-standard, high image-reject front-end is presented. The fr... more In this paper, the analysis of a multi-standard, high image-reject front-end is presented. The front-end is designed to be used for Digital European Cordless Telephone (DECT) systems and wireless communications systems, which operate in the 2.4 GHz Industrial Scientific Medical (ISM) band (like Bluetooth). A double-quadrature low-IF architecture is chosen, because it can provide a high image rejection ratio (IRR)

RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE Radio Frequency integrated Circuits

Abstract Two I/Q oscillators have been realized that cover a one octave tuning range, and, when c... more Abstract Two I/Q oscillators have been realized that cover a one octave tuning range, and, when combined with a divider and a multiplexer, cover the complete TV band. The realized oscillators embody highly cost-effective key building blocks for tuning systems in ...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) ... more A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

Analog Circuits and Signal Processing, 2014

DOI to the publisher's website. • The final author version and the galley proof are versions of t... more DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

Communications Engineer, 2003

DVB-T is a transmission standard that enables good reception even when the transmission channel i... more DVB-T is a transmission standard that enables good reception even when the transmission channel is subject to frequency-selective fading. When DVB-T is used for a mobile microwave link, flat fading can occasionally occur. In this article, a time interleaving layer is proposed that makes the transmission more rugged under flat fading conditions. The proposed mechanism involves an additional Reed-Solomon coding step and a modified data transmission order, and preserves the DVB-T layer of the communications channel. This document was originally published in IEE Communications Engineer (June/July 2003).

Wide-Bandwidth High-Dynamic Range D/A Converters

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011

This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM... more This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM band and implemented in 45nm CMOS technology. The PA is based on a distributed active transformer (DAT) topology which enables simultaneous power combining and realization of an efficient impedance matching. To cope with the asymmetric nature of DAT, resulting in common-mode and unequal differential voltage-swings at its input-ports, this paper presents two universal methods which do not impose any layout restrictions and layout adjustments. The realized PA achieves 13.2dBm output power at 1dB compression, a saturated output power of 16.3dBm, a PAE of 8.7% and 18.7dBm OIP3, while consuming 178mA at 1.8V.

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

This paper presents a new on-chip low-power selfcalibration apparatus implemented in a 12-bit cur... more This paper presents a new on-chip low-power selfcalibration apparatus implemented in a 12-bit currentsteering 250nm CMOS DAC. The DAC core consists of a non-calibrated binary LSB part and a calibrated thermometer MSB part. The thermometer currents are generated by combining a coarse 10-bit accurate current with a fine calibrating current provided by a small calibrating DAC (CALDAC). The magnitude of the fine current is determined in the digital domain and optimized for overall post-calibration accuracy. This digital process acquires mismatch error information from on an on-chip single bit ADC. The whole calibration process is executed once at chip power-up and the calibration results are recorded. During the normal operation of the DAC, no active calibration operations are present and the fine currents are kept static, so that the advantages of calibration are maintained even at very high conversion rates. The self-calibrated DAC achieves 12-bit static and dynamic linearity, while occupying smaller silicon area due to the intrinsic 10-bit accuracy of the DAC core.

2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), 2016

This paper presents a LED driver based on a new Hybrid-Switched Capacitor Converter (H-SCC) opera... more This paper presents a LED driver based on a new Hybrid-Switched Capacitor Converter (H-SCC) operating in the MHz range, which uses the internal pulsed nodes of a Dickson converter and an LC output network to provide output current dimming. The converter is implemented using 5V integrated capacitors and switches in a 0.18μm bulk CMOS technology. The experimental results show that the proposed LED driver has a power density of 122mW/mm2 and an efficiency of 79%, and only needs a small 40nH inductor.

IEEE MTT-S International Microwave Symposium Digest, 2003, 2003

In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varyin... more In this paper phase shift tuning of a 5.3 GHz quadrature LC oscillator is investigated. By varying the phase shift of the circuits that couple two LC oscillator stages, a 1.1 GHz: tuning range is achieved. Dependency of tuning range and phase noise on the quality factor of the LC resonators is explored on the behavioral level. Expressions are given for the tuning range and an effective quality factor, as a function of the resonator quality, its phase shift and its resonance frequency. The oscillator is realized in a mainstream 30 GHz f/sub T/ BiCMOS process and dissipates 45 mW (nominal) with 2.7 V supply voltage. The dependency of the tuning range on the resonator quality is measured by varying the quality factor of a varactor incorporated in the LC resonators of the I/Q oscillator. Measured /spl Lscr/(2 MHz) is -108 dBc/Hz at 5.6 GHz.

Wide-Bandwidth High-Dynamic Range D/A Converters

A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB r... more A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.

80th ARFTG Microwave Measurement Conference, 2012

This paper describes a novel broadband hybrid load-and source-pull system. It eliminates the need... more This paper describes a novel broadband hybrid load-and source-pull system. It eliminates the need for a variable attenuator and variable phase-shifter and it employs the conventional passive tuner calibration procedure. It is established around a Gamma Boosting Unit (GBU), which is composed of two directional couplers and an auxiliary amplifier and which resembles a positive feedback loop. Device measurements at 900MHz and 30GHz demonstrate a significant improvement for the measured output efficiency and transducer gain.

9th International Conference on Electronics, Circuits and Systems

In this paper, the analysis of a multi-standard, high image-reject front-end is presented. The fr... more In this paper, the analysis of a multi-standard, high image-reject front-end is presented. The front-end is designed to be used for Digital European Cordless Telephone (DECT) systems and wireless communications systems, which operate in the 2.4 GHz Industrial Scientific Medical (ISM) band (like Bluetooth). A double-quadrature low-IF architecture is chosen, because it can provide a high image rejection ratio (IRR)

RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE Radio Frequency integrated Circuits

Abstract Two I/Q oscillators have been realized that cover a one octave tuning range, and, when c... more Abstract Two I/Q oscillators have been realized that cover a one octave tuning range, and, when combined with a divider and a multiplexer, cover the complete TV band. The realized oscillators embody highly cost-effective key building blocks for tuning systems in ...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) ... more A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

Analog Circuits and Signal Processing, 2014

DOI to the publisher's website. • The final author version and the galley proof are versions of t... more DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement: