Ashish Mishra - Academia.edu (original) (raw)
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Papers by Ashish Mishra
Ijca Proceedings on Recent Advances in Wireless Communication and Artificial Intelligence, Sep 29, 2014
Voltage Controlled Oscillator (VCO) is an important building block in wireless communication syst... more Voltage Controlled Oscillator (VCO) is an important building block in wireless communication system. In this paper a five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed which is used in Phase Lock Loop (PLL). The design is implemented on CADENCE VIRTUOSO Platform with high oscillation frequency and low power dissipation. The oscillation frequency of the designed VCO ranges from (665.7MHz-1.128GHz). The circuit is simulated using 180nm CMOS Technology. Simulation result shows that the power dissipation is-12dBm at power supply of 1.8 volt and the phase noise is (-105dBc/Hz @ 10MHz offset). The designing of such VCO shows the efficient performance of the oscillator circuit under given conditions. Such design is useful for frequency synthesizer application in PLL with less design cost.
2014 International Conference on Signal Propagation and Computer Technology (ICSPCT 2014), 2014
ABSTRACT This paper presents the design of PLL (Phase Locked Loop) using PFD (Phase Frequency Det... more ABSTRACT This paper presents the design of PLL (Phase Locked Loop) using PFD (Phase Frequency Detector) based on 22 transistors TSPC (True Single Phase Clock) D-FF (Flip Flop), Tri-state charge pump (CP), passive loop filter of first order and five- stage CS-VCO (Current Starved VCO) circuit. In such design, large VCO gain with increased lock range from (357MHz-900MHz) and reduced lock time is achieved using first order passive lag loop filter. The oscillation frequency range (431.683 MHz-1.7966 GHz) for VCO is increased due to reduced number of inverter stages and power dissipated by overall PLL is getting improved (7.08mW) with less design cost. Area occupied by such PLL is also reduced. This reduction in area and power is achieved with the help of five-stage CS-VCO instead of LC-Tank VCO and five-stage multiple pass ring VCO [8],[12]. The prototype is simulated using 0.18um CMOS technology with supply voltage of 1.8V. In such context the lock time of 54ns is achieved by properly selecting the design parameters for low pass filter (R and C) with reasonable damping factor (ζ=0.7).
2015 Annual IEEE India Conference (INDICON), 2015
This paper presents a method for designing of low power dissipation, low phase noise and high osc... more This paper presents a method for designing of low power dissipation, low phase noise and high oscillation frequency based three stage Current Starved VCO (CS-VCO). In this design approach, 3-inverter stages are cascaded to achieve an optimal power dissipation of (7.48508 mW) for fundamental frequency of (3.9955 GHz). The simulation results depict that such VCO has linear voltage-frequency characteristics over a wide tuning range. The circuit performance is validated using 0.18μm CMOS technology. The analysis also shows that for 3-stage CS-VCO, the phase noise is -80.17dbc/Hz @1MHz offset frequency and -105.31dbc/Hz @10MHz offset frequency.
Ijca Proceedings on Recent Advances in Wireless Communication and Artificial Intelligence, Sep 29, 2014
Voltage Controlled Oscillator (VCO) is an important building block in wireless communication syst... more Voltage Controlled Oscillator (VCO) is an important building block in wireless communication system. In this paper a five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed which is used in Phase Lock Loop (PLL). The design is implemented on CADENCE VIRTUOSO Platform with high oscillation frequency and low power dissipation. The oscillation frequency of the designed VCO ranges from (665.7MHz-1.128GHz). The circuit is simulated using 180nm CMOS Technology. Simulation result shows that the power dissipation is-12dBm at power supply of 1.8 volt and the phase noise is (-105dBc/Hz @ 10MHz offset). The designing of such VCO shows the efficient performance of the oscillator circuit under given conditions. Such design is useful for frequency synthesizer application in PLL with less design cost.
2014 International Conference on Signal Propagation and Computer Technology (ICSPCT 2014), 2014
ABSTRACT This paper presents the design of PLL (Phase Locked Loop) using PFD (Phase Frequency Det... more ABSTRACT This paper presents the design of PLL (Phase Locked Loop) using PFD (Phase Frequency Detector) based on 22 transistors TSPC (True Single Phase Clock) D-FF (Flip Flop), Tri-state charge pump (CP), passive loop filter of first order and five- stage CS-VCO (Current Starved VCO) circuit. In such design, large VCO gain with increased lock range from (357MHz-900MHz) and reduced lock time is achieved using first order passive lag loop filter. The oscillation frequency range (431.683 MHz-1.7966 GHz) for VCO is increased due to reduced number of inverter stages and power dissipated by overall PLL is getting improved (7.08mW) with less design cost. Area occupied by such PLL is also reduced. This reduction in area and power is achieved with the help of five-stage CS-VCO instead of LC-Tank VCO and five-stage multiple pass ring VCO [8],[12]. The prototype is simulated using 0.18um CMOS technology with supply voltage of 1.8V. In such context the lock time of 54ns is achieved by properly selecting the design parameters for low pass filter (R and C) with reasonable damping factor (ζ=0.7).
2015 Annual IEEE India Conference (INDICON), 2015
This paper presents a method for designing of low power dissipation, low phase noise and high osc... more This paper presents a method for designing of low power dissipation, low phase noise and high oscillation frequency based three stage Current Starved VCO (CS-VCO). In this design approach, 3-inverter stages are cascaded to achieve an optimal power dissipation of (7.48508 mW) for fundamental frequency of (3.9955 GHz). The simulation results depict that such VCO has linear voltage-frequency characteristics over a wide tuning range. The circuit performance is validated using 0.18μm CMOS technology. The analysis also shows that for 3-stage CS-VCO, the phase noise is -80.17dbc/Hz @1MHz offset frequency and -105.31dbc/Hz @10MHz offset frequency.