Azhar Mohammad - Academia.edu (original) (raw)

Papers by Azhar Mohammad

Microelectronics Journal, 2017

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficien... more With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as radio frequency identification tags and wireless sensor nodes employ AES cryptographic module that are susceptible to differential power analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic device increases, which increases their vulnerability to DPA attack. This paper presents a novel FinFET-based secure adiabatic logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a positive polarity Reed Muller architecture-based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL (20-nm FinFET technology) S-box circuit saves up to 81% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET (20-nm FinFET technology). Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, the impact of FinSAL on hardware security at different technology nodes of FinFETs (7, 10, 14, and 16 nm) are evaluated. From the simulation results, FinSAL gates at 14-nm FinFET offer superior security with optimum power consumption, therefore is the best candidate to design low-power secure IoT devices.

IEEE Transactions on Emerging Topics in Computing, 2016

The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identificati... more The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identification (RFID) and smart cards that are energy-efficient and secure against Differential Power Analysis (DPA) attacks. Adiabatic logic is one of the circuit design techniques that can be used to design energy-efficient and secure hardware. However, the existing DPA resistant adiabatic logic families suffer from non-adiabatic energy loss. Therefore, this work presents a novel adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) family that reduces the non-adiabatic energy loss and also is secure against DPA attacks. The proposed EE-SPFAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on EE-SPFAL are used to implement a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that EE-SPFAL based S-box circuit saves up to 65 percent of energy and 90 percent of energy per cycle as compared to the S-box circuit implemented using existing Secured Quasi-Adiabatic Logic (SQAL) and conventional CMOS logic, respectively. Further, the security of EE-SPFAL based S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the EE-SPFAL based S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, we have implemented the one round of Advanced Standard Encryption (AES) algorithm and we found that one round of EE-SPFAL logic based AES consumes uniform current with different input plain texts. Low energy consumption and security against DPA attacks makes EE-SPFAL logic a suitable candidate to implement in IoT devices such as RFID and smart cards.

2016 IEEE International Conference on Rebooting Computing (ICRC), 2016

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficien... more With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as Radio Frequency Identification (RFID) tags and Wireless Sensor Nodes (WSN) employ AES cryptographic modules that are susceptible to Differential Power Analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic devices increases, which increases the vulnerability to DPA attacks. This paper presents a novel FinFET based Secure Adiabatic Logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a Positive Polarity Reed Midler (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL S-box circuit saves up to 84% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET. Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations.

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

Differential Power Analysis (DPA) attack is considered to be a main threat while designing crypto... more Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for low power portable electronic devices and Internet-of-Things (IoT) based electronic devices.

OF THESIS EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS The growing a... more OF THESIS EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on three of those emerging and novel low power design techniques namely Adiabatic logic and Magnetic Tunnel Junction (MTJ) logic and Carbon Nanotube Field Effect transistor (CNFET) logic. Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.

Microelectronics Journal, 2017

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficien... more With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as radio frequency identification tags and wireless sensor nodes employ AES cryptographic module that are susceptible to differential power analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic device increases, which increases their vulnerability to DPA attack. This paper presents a novel FinFET-based secure adiabatic logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a positive polarity Reed Muller architecture-based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL (20-nm FinFET technology) S-box circuit saves up to 81% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET (20-nm FinFET technology). Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, the impact of FinSAL on hardware security at different technology nodes of FinFETs (7, 10, 14, and 16 nm) are evaluated. From the simulation results, FinSAL gates at 14-nm FinFET offer superior security with optimum power consumption, therefore is the best candidate to design low-power secure IoT devices.

IEEE Transactions on Emerging Topics in Computing, 2016

The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identificati... more The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identification (RFID) and smart cards that are energy-efficient and secure against Differential Power Analysis (DPA) attacks. Adiabatic logic is one of the circuit design techniques that can be used to design energy-efficient and secure hardware. However, the existing DPA resistant adiabatic logic families suffer from non-adiabatic energy loss. Therefore, this work presents a novel adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) family that reduces the non-adiabatic energy loss and also is secure against DPA attacks. The proposed EE-SPFAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on EE-SPFAL are used to implement a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that EE-SPFAL based S-box circuit saves up to 65 percent of energy and 90 percent of energy per cycle as compared to the S-box circuit implemented using existing Secured Quasi-Adiabatic Logic (SQAL) and conventional CMOS logic, respectively. Further, the security of EE-SPFAL based S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the EE-SPFAL based S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, we have implemented the one round of Advanced Standard Encryption (AES) algorithm and we found that one round of EE-SPFAL logic based AES consumes uniform current with different input plain texts. Low energy consumption and security against DPA attacks makes EE-SPFAL logic a suitable candidate to implement in IoT devices such as RFID and smart cards.

2016 IEEE International Conference on Rebooting Computing (ICRC), 2016

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficien... more With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as Radio Frequency Identification (RFID) tags and Wireless Sensor Nodes (WSN) employ AES cryptographic modules that are susceptible to Differential Power Analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic devices increases, which increases the vulnerability to DPA attacks. This paper presents a novel FinFET based Secure Adiabatic Logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a Positive Polarity Reed Midler (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL S-box circuit saves up to 84% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET. Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations.

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

Differential Power Analysis (DPA) attack is considered to be a main threat while designing crypto... more Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for low power portable electronic devices and Internet-of-Things (IoT) based electronic devices.

OF THESIS EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS The growing a... more OF THESIS EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on three of those emerging and novel low power design techniques namely Adiabatic logic and Magnetic Tunnel Junction (MTJ) logic and Carbon Nanotube Field Effect transistor (CNFET) logic. Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.