Baskaran Ganesan - Academia.edu (original) (raw)
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Zentrum für Literatur- und Kulturforschung, Berlin
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Dans un mode de realisation de l'invention, un processeur comprend plusieurs cœurs pour execu... more Dans un mode de realisation de l'invention, un processeur comprend plusieurs cœurs pour executer des fils. Le processeur comprend egalement une logique de controle de puissance pour permettre une entree dans un mode turbo d'apres une comparaison entre un seuil et une valeur d'un compteur qui enregistre un nombre de combinaisons de puissance et de performance de cœur qui identifient des demandes de mode turbo d'au moins un des fils. De cette maniere, il est possible d'entrer dans le mode turbo a un niveau d'utilisation du processeur qui fournit une efficacite energetique elevee. L'invention concerne d'autres modes de realisation.
EP O 427 O73 A2 5/1991 EP O 665 293 A2 8/1995 EP O 721 O16 A2 7/1996 EP O 853 129 A2 7/1998 EP O ... more EP O 427 O73 A2 5/1991 EP O 665 293 A2 8/1995 EP O 721 O16 A2 7/1996 EP O 853 129 A2 7/1998 EP O 995 804 A2 4/2000 WO WO 89/03432 4/1989 WO WO 90/13666 11/1990 WO WO 93/21340 10/1993 WO WO95/20053 7/1995 WO WO 96/27025 9/1996 WO WO 96/36731 11/1996 WO WO 97/04131 2/1997 WO WO 97/08183 3/1997 WO 97/27317 * 7/1997 WO WO 98/03673 1/1998 WO WO 98/20019 5/1998 WO WO 98/29376 7/1998 WO WO 99/O5315 2/1999 WO WO 99/O5321 2/1999 WO WO 99/28494 6/1999 WO WO 99/28505 6/1999
In one embodiment, a processor on a plurality of cores to execute threads. The processor further ... more In one embodiment, a processor on a plurality of cores to execute threads. The processor further includes a power control logic to entry into a turbo-mode based on a comparison between a threshold value and the value of a counter, which identify a count of the core service and stores power combinations that Turbo mode requests from at least one of the threads , to activate. In this way, can be entered at a utilization rate of the processor in Turbo mode which provides higher energy efficiency. Other embodiments are described and claimed.
A multi-core processor, comprising: a plurality of cores (110) and an uncore, said the uncore hav... more A multi-core processor, comprising: a plurality of cores (110) and an uncore, said the uncore having at least one cache memory, a plurality of logic units, comprising a router (130), a power control unit (150) and at least one further logic unit, wherein the power control unit (150) comprises at least one of the plurality of logic units and the target tick control a cache memory of the uncore at least when the multi-core processor is in a low power state after a first time period has occurred in which the plurality of logic units was permanently cleared transactions prevented after the transactions on a first channel were, and after a second time period has occurred in which the plurality of logic units was continuously emptied of transactions, wherein the power control unit is designed to prevent incoming transactions from one or more channels outside of the socket prior to the clock controlling.
Dans un mode de realisation de l'invention, un processeur comprend plusieurs cœurs pour execu... more Dans un mode de realisation de l'invention, un processeur comprend plusieurs cœurs pour executer des fils. Le processeur comprend egalement une logique de controle de puissance pour permettre une entree dans un mode turbo d'apres une comparaison entre un seuil et une valeur d'un compteur qui enregistre un nombre de combinaisons de puissance et de performance de cœur qui identifient des demandes de mode turbo d'au moins un des fils. De cette maniere, il est possible d'entrer dans le mode turbo a un niveau d'utilisation du processeur qui fournit une efficacite energetique elevee. L'invention concerne d'autres modes de realisation.
EP O 427 O73 A2 5/1991 EP O 665 293 A2 8/1995 EP O 721 O16 A2 7/1996 EP O 853 129 A2 7/1998 EP O ... more EP O 427 O73 A2 5/1991 EP O 665 293 A2 8/1995 EP O 721 O16 A2 7/1996 EP O 853 129 A2 7/1998 EP O 995 804 A2 4/2000 WO WO 89/03432 4/1989 WO WO 90/13666 11/1990 WO WO 93/21340 10/1993 WO WO95/20053 7/1995 WO WO 96/27025 9/1996 WO WO 96/36731 11/1996 WO WO 97/04131 2/1997 WO WO 97/08183 3/1997 WO 97/27317 * 7/1997 WO WO 98/03673 1/1998 WO WO 98/20019 5/1998 WO WO 98/29376 7/1998 WO WO 99/O5315 2/1999 WO WO 99/O5321 2/1999 WO WO 99/28494 6/1999 WO WO 99/28505 6/1999
In one embodiment, a processor on a plurality of cores to execute threads. The processor further ... more In one embodiment, a processor on a plurality of cores to execute threads. The processor further includes a power control logic to entry into a turbo-mode based on a comparison between a threshold value and the value of a counter, which identify a count of the core service and stores power combinations that Turbo mode requests from at least one of the threads , to activate. In this way, can be entered at a utilization rate of the processor in Turbo mode which provides higher energy efficiency. Other embodiments are described and claimed.
A multi-core processor, comprising: a plurality of cores (110) and an uncore, said the uncore hav... more A multi-core processor, comprising: a plurality of cores (110) and an uncore, said the uncore having at least one cache memory, a plurality of logic units, comprising a router (130), a power control unit (150) and at least one further logic unit, wherein the power control unit (150) comprises at least one of the plurality of logic units and the target tick control a cache memory of the uncore at least when the multi-core processor is in a low power state after a first time period has occurred in which the plurality of logic units was permanently cleared transactions prevented after the transactions on a first channel were, and after a second time period has occurred in which the plurality of logic units was continuously emptied of transactions, wherein the power control unit is designed to prevent incoming transactions from one or more channels outside of the socket prior to the clock controlling.