Valeriu Beiu - Academia.edu (original) (raw)

Papers by Valeriu Beiu

Springer eBooks, Jul 28, 2020

In this paper we compute the coefficients of the reliability polynomial of a consecutive-k-out-of... more In this paper we compute the coefficients of the reliability polynomial of a consecutive-k-out-of-n:F system, in Bernstein basis, using the generalized Pascal coefficients. Based on well-known combinatorial properties of the generalized Pascal triangle we determine simple closed formulae for the reliability polynomial of a consecutive system for particular ranges of k. Moreover, for the remaining ranges of k (where we were not able to determine simple closed formulae), we establish easy to calculate sharp bounds for the reliability polynomial of a consecutive system.

arXiv (Cornell University), Mar 27, 2020

arXiv (Cornell University), Nov 4, 2019

In this article, we take a closer look at the reliability of large minimal networks constructed b... more In this article, we take a closer look at the reliability of large minimal networks constructed by repeated compositions of the simplest possible networks. For a given number of devices n = 2 m we define the set of all the possible compositions of series and parallel networks of two devices. We then define several partial orders over this set and study their properties. As far as we know the ranking problem has not been addressed before in this context, and this article establishes the first results in this direction. The usual approach when dealing with reliability of two-terminal networks is to determine existence or non-existence of uniformly most reliable networks. The problem of ranking two-terminal networks is thus more complex, but by restricting our study to the set of compositions we manage to determine and demonstrate the existence of a poset.

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006

Journal of Low Power Electronics, 2014

ABSTRACT This paper analyzes in details a novel transistor sizing method for classical CMOS gates... more ABSTRACT This paper analyzes in details a novel transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating correctly over the whole voltage range, including ultra-low voltages. The method proposed recently relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). In this paper we use five classical CMOS gates (INV, NAND-2, NOR-2, XOR-2, MAJ-3) for evaluating and comparing performances. Monte Carlo simulations are used for the first time for these gates and sizing method. The Monte Carlo simulation results show that the sizing method is able to improve even more than what was known from previous simulations (which did not consider statistical variations). This also proves that sizing in very fine increments has the potential to go beyond the well-established delay-power tradeoff, as it can significantly increase SNM's while also reducing power, and in many cases reducing the power-delay-product (PDP) also. Simulation results show that the sizing method enables much more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence potentially paving the way to ultra-low voltage/power/energy circuits.

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013

ABSTRACT This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized b... more ABSTRACT This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized both conventionally as well as unconventionally. The reason is that ST INVs are using positive feedback (which leads to hysteresis) and are expected to exhibit much better static noise margins (SNMs) than classical CMOS INVs. That is why ST INVs are more reliable. Lately, quite a few papers have been looking at using ST INVs for implementing SRAMs focusing mainly on the ultra-low voltage/power application range. Here we are going to look at SNM, delay, power and power-delay-product over the whole voltage range for exploring the potential advantages ST could offer in advanced CMOS technology nodes, and better identify their application range.

2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486)

This paper details a systematic method for significantly improving the noise margins of very fast... more This paper details a systematic method for significantly improving the noise margins of very fast threshold gates, by adding nonlinear terms determined from the Boolean form of the function to be implemented. Simulation results support our theoretical claims. Methods for reducing the power consumption are also suggested

2009 International Conference on Innovations in Information Technology (IIT), 2009

ABSTRACT The high-level approach for estimating circuit reliability tends to consider the probabi... more ABSTRACT The high-level approach for estimating circuit reliability tends to consider the probability of failure of a logic gate as a constant, and work towards the higher levels. With scaling, such gate-centric approaches become highly inaccurate, as both transistors and input vectors drastically affect the probability of failure of the logic gates. This paper will present a transistor-level gate failure analysis starting from threshold voltage variations. We will briefly review the state-of-the-art, and rely upon freshly reported results for threshold voltage variations. These will be used to estimate the probabilities of failure of a classical NAND-2 CMOS gate for (a few) different technologies, voltages, and input vectors. They will also reveal huge differences between the highest and the lowest probabilities of failure, and will show how strongly these are affected by the supply voltage.

2011 11th IEEE International Conference on Nanotechnology, 2011

Full adders (FAs) are essential for digital circuits including microprocessors, digital signal pr... more Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers. Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (VTH) variations play on the reliability of a classical 28-transistor FA, and

Proceedings. VLSI and Computer Peripherals. COMPEURO 89

The authors consider vision from a neural-network (NN) point of view. After describing the struct... more The authors consider vision from a neural-network (NN) point of view. After describing the structure of the human retina and its neurons, a general model of NNs is presented. For color, patterns, and motion detection, a three-layer NN is detailed. Further, three variable-threshold NNs (color identification) are introduced. The detection of motion is also done in this second layer using already preprocessed information represented by on-off, on, and off signals, with the same meaning as the corresponding signals from the human ganglion cells; four analog classifiers are used for directions (up, down, left, right). The results of a program used to simulate the proposed NN are discussed, as well as a theoretical VLSI implementation. It is shown that a complete graph having n nodes can be laid out in an almost square area of O(n/sup 2/), with O(n) wire length.<<ETX>>

International Symposium on Quality Electronic Design (ISQED), 2013

ABSTRACT This paper suggests a transistor sizing method for classical CMOS gates implemented in a... more ABSTRACT This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The method relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (INV, NAND-2, NOR-2) for introducing the novel sizing method, as well as for validating the concept and evaluating its performances. The results show that sizing has not entirely exhausted its potential, allowing to go beyond the well established delay-power tradeoff, as sizing can increase SNMs by: (i) adjusting the threshold voltages (VTH) and their variations (σVTH); and (ii) balancing the VTCs. Simulation results show that this sizing method enables more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence leading to ultra-low voltage/power circuits.

CAS 2013 (International Semiconductor Conference), 2013

This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the lengt... more This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (V th) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that V th and L change by ~2%, while SNM's increase by ~30%, with power and energy being reduced ~10× and ~20× respectively. I.

IEEE International Conference on Computer Systems and Applications, 2006., 2006

This paper investigates multiplexing schemes in single-electron technology (SET). The study focus... more This paper investigates multiplexing schemes in single-electron technology (SET). The study focuses on the behavior of two multiplexing schemes in combination with gates subject to geometric variations affecting their elementary components (capacitors). The two schemes under investigation are MAJORITY- and NANDmultiplexing. First, the elementary gates are compared in terms of their intrinsic probability of failure with respect to variations. Secondly,

2006 Sixth IEEE Conference on Nanotechnology

This paper investigates the behavior of multiplexing schemes in combination with elementary gates... more This paper investigates the behavior of multiplexing schemes in combination with elementary gates. The two schemes under investigation are MAJORITY- and NAND-multiplexing. The simulation results are for single-electron technology (SET), where the elementary components of the gates (capacitors in the case of capacitive-SET) are subjected to geometric variations. First, the elementary gates are compared in terms of their intrinsic probability

IEEE Transactions on Reliability, 2011

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very succes... more Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the function- ality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges as- sociated

IEEE Transactions on Reliability, 2012

ABSTRACT Introducing redundancy at the device-level has been proposed as the most effective way t... more ABSTRACT Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 105, 10, and 1010 respectively, while the area is increased by less than 50%.

IEEE Transactions on Nanotechnology, 2011

This paper starts by reviewing many of the gate-level reliability analyses of von Neumann multipl... more This paper starts by reviewing many of the gate-level reliability analyses of von Neumann multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology specific) analyses of vN-MUX with respect to threshold voltage variations, taking into account both the gates&amp;amp;amp;amp;amp;amp;amp;#x27; topology as well as the input vectors. Such results are essential for a clear understand- ing of vN-MUX

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012

Generic as well as customized reliability electronic design automation (EDA) tools have been prop... more Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PFrmGATE=const.)({PF}_{\rm GATE}=const.)(PFrmGATE=const.) , or 2)