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Papers by Benjamin Gittins

IACR Cryptology ePrint Archive, 2007

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

This paper is a preliminary report on the static-timing, R-Cell, die-area and static-power requir... more This paper is a preliminary report on the static-timing, R-Cell, die-area and static-power requirements of the complete data-path of VEST-32 ciphers on LSI Logic RapidChip 180nm and 110nm Technologies. Based on the conservative standard RapidChip design front-end sign-off process, VEST-32 can effortlessly satisfy a demand for 256-bit secure 10 Gb/s authenticated encryption @ 167 MHz on 180nm LSI Logic RapidChip platform ASIC technologies in less than 45K Gates and zero SRAM. On the 110nm Rapidchip technologies, VEST-32 offers 20 Gb/s authenticated encryption @ 320 MHz in less than 45 K gates. Similar bandwidth performance may be achievable with reduced circuit area using a custom sign-off process.

VEST A multi-purpose cryptographic primitive with integrated family keying support providing encr... more VEST A multi-purpose cryptographic primitive with integrated family keying support providing encryption, keyed message authentication and collision resistant hashing, targeted to semi-conductor applications

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

Modern societies are almost totally dependent upon cyber systems that are not safe or secure. To ... more Modern societies are almost totally dependent upon cyber systems that are not safe or secure. To paraphrase [7] the Director of the U.S. National Security Agency (NSA): there is no such thing as secure anymore... we must assume the attacker is or can get inside our systems (2010). Successful cyber-physical attacks can strike instantly, destroying critical infrastructure, including nuclear power facilities (e.g. Stuxnet virus) [8]. Many cyber attacks defy accurate attribution [4]. They can gain access to top secret intelligence, industrial control systems, components required to support and/or build nuclear bombs, and so on [20]. Due to the scale of potential (financial and physical) damage from such cyber attacks, any of these activities could fuel an escalation to nuclear war – particularly if physical destruction coincides with a conventional conflict situation [22]. See [23] for global cyber status survey. As demonstrated by the recent strategy driven nonviolent struggles around ...

In 2007, the E.U. FP6 SecurIST called [31] for trustworthy international identity management (IdM... more In 2007, the E.U. FP6 SecurIST called [31] for trustworthy international identity management (IdM) that was usercentric.

Abstract. VEST is a set of four stream cipher families targeted to semiconductor applications. Al... more Abstract. VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

2 Author Biographies 4 Introduction 5 Security is Essential for Safety 5 Programmable FPGA device... more 2 Author Biographies 4 Introduction 5 Security is Essential for Safety 5 Programmable FPGA devices should be included in Security Risk Assessments 6 What are FPGA devices? 6 Where can FPGA’s be found? 7 Why are FPGAs vulnerable? 7 FPGA attacks can come from inside and outside an organisation 8 Awareness of low-cost FPGA vulnerability is increasing, making attacks more likely 9 The role of external audit firms 9 Five elements to consider in exploring an FPGA risk assessment audit 10 A base-line level of FPGA security can be readily achieved today at low cost 12 What organizations must do today 13 What audit firms should do today 13 Conclusion 14 Contact 15 References 15

This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ... more This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ciphers operating in the authenticated encryption mode with infinite error propagation provide keyed message authentication at the same speed as their keystream generation, with negligible overhead and maintaining their security ratings.

... The IdM-CKM proposal as described in this paper pro-tects clients from security compromises a... more ... The IdM-CKM proposal as described in this paper pro-tects clients from security compromises as a result of latent vulnerabilities or malware present in the software or hard-ware used by IdM-CKM service providers, or by the service provider's privileged technical or managerial ...

Lecture Notes in Computer Science, 2012

In this paper we study how to generate new secret key block ciphers based on the AES and Feistel ... more In this paper we study how to generate new secret key block ciphers based on the AES and Feistel constructions, that allow arbitrary large input/output lengths while maintaining the ability to select-a priori-arbitrary security levels. We start from the generation of block ciphers that are simple balanced Feistel constructions that exploit the pseudorandomness of functions, namely the AES, as round function. This results in block ciphers with inputs and outputs of size 256 bits, i.e., that are doubled compared to the AES. We then extend this principle following the "Russian Doll" design principle to build block ciphers with (arbitrarily) larger inputs and outputs. As an example, we build block ciphers with an expected security in about 2 512 , or 2 1024 , instead of 2 128 for the classical AES with 128 key-bits. The expected security is not proven, but our constructions are based on the best known attacks against Feistel networks with internal random permutations, as well as some natural security assumptions. We study two configurations of assumptions, leading to two families of simple and efficient new block ciphers, which can thus be seen as candidate schemes for higher security.

VEST hardware-dedicated stream ciphers are based on bijective non- linear parallel feedback shift... more VEST hardware-dedicated stream ciphers are based on bijective non- linear parallel feedback shift registers assisted by non-linear Remainder Number System (RNS) based counters. Three VEST cipher family trees are introduced: VEST-4, VEST-16 and VEST-32. VEST-4 returning 4 bits of output per clock cycle occupying ~4K ASIC gates offers 80-bit security, perfect for low-area low-cost applications such as RFID and smartcards. VEST-16 returning 16 bits of output per clock cycle occupying ~12K ASIC gates offers 160-bit security, perfect for high-speed low-area low cost applications. VEST-32 returning 32 bits of output per clock cycle occupying ~20K ASIC gates offers 256-bit security, perfect for high-speed high security applications such as processor-bus encryption. All VEST ciphers support variable key sizes and instant re-keying, and all VEST ciphers release output on every clock cycle.

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-... more VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-linear Residue Number System (RNS) based counters. Four VEST cipher family trees are introduced: 80-bit secure VEST-4, 128-bit secure VEST-8, 160-bit secure VEST-16 and 256-bit secure VEST-32. VEST ciphers return 4 to 32 bits of output per clock cycle while occupying ~5K to ~22K ASIC gates including

This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ... more This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ciphers operating in the authenticated encryption mode with infinite error propagation provide keyed message authentication at the same speed as their keystream generation, with negligible overhead and maintaining their security ratings.

IACR Cryptology ePrint Archive, 2007

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

This paper is a preliminary report on the static-timing, R-Cell, die-area and static-power requir... more This paper is a preliminary report on the static-timing, R-Cell, die-area and static-power requirements of the complete data-path of VEST-32 ciphers on LSI Logic RapidChip 180nm and 110nm Technologies. Based on the conservative standard RapidChip design front-end sign-off process, VEST-32 can effortlessly satisfy a demand for 256-bit secure 10 Gb/s authenticated encryption @ 167 MHz on 180nm LSI Logic RapidChip platform ASIC technologies in less than 45K Gates and zero SRAM. On the 110nm Rapidchip technologies, VEST-32 offers 20 Gb/s authenticated encryption @ 320 MHz in less than 45 K gates. Similar bandwidth performance may be achievable with reduced circuit area using a custom sign-off process.

VEST A multi-purpose cryptographic primitive with integrated family keying support providing encr... more VEST A multi-purpose cryptographic primitive with integrated family keying support providing encryption, keyed message authentication and collision resistant hashing, targeted to semi-conductor applications

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

Modern societies are almost totally dependent upon cyber systems that are not safe or secure. To ... more Modern societies are almost totally dependent upon cyber systems that are not safe or secure. To paraphrase [7] the Director of the U.S. National Security Agency (NSA): there is no such thing as secure anymore... we must assume the attacker is or can get inside our systems (2010). Successful cyber-physical attacks can strike instantly, destroying critical infrastructure, including nuclear power facilities (e.g. Stuxnet virus) [8]. Many cyber attacks defy accurate attribution [4]. They can gain access to top secret intelligence, industrial control systems, components required to support and/or build nuclear bombs, and so on [20]. Due to the scale of potential (financial and physical) damage from such cyber attacks, any of these activities could fuel an escalation to nuclear war – particularly if physical destruction coincides with a conventional conflict situation [22]. See [23] for global cyber status survey. As demonstrated by the recent strategy driven nonviolent struggles around ...

In 2007, the E.U. FP6 SecurIST called [31] for trustworthy international identity management (IdM... more In 2007, the E.U. FP6 SecurIST called [31] for trustworthy international identity management (IdM) that was usercentric.

Abstract. VEST is a set of four stream cipher families targeted to semiconductor applications. Al... more Abstract. VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

2 Author Biographies 4 Introduction 5 Security is Essential for Safety 5 Programmable FPGA device... more 2 Author Biographies 4 Introduction 5 Security is Essential for Safety 5 Programmable FPGA devices should be included in Security Risk Assessments 6 What are FPGA devices? 6 Where can FPGA’s be found? 7 Why are FPGAs vulnerable? 7 FPGA attacks can come from inside and outside an organisation 8 Awareness of low-cost FPGA vulnerability is increasing, making attacks more likely 9 The role of external audit firms 9 Five elements to consider in exploring an FPGA risk assessment audit 10 A base-line level of FPGA security can be readily achieved today at low cost 12 What organizations must do today 13 What audit firms should do today 13 Conclusion 14 Contact 15 References 15

This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ... more This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ciphers operating in the authenticated encryption mode with infinite error propagation provide keyed message authentication at the same speed as their keystream generation, with negligible overhead and maintaining their security ratings.

... The IdM-CKM proposal as described in this paper pro-tects clients from security compromises a... more ... The IdM-CKM proposal as described in this paper pro-tects clients from security compromises as a result of latent vulnerabilities or malware present in the software or hard-ware used by IdM-CKM service providers, or by the service provider's privileged technical or managerial ...

Lecture Notes in Computer Science, 2012

In this paper we study how to generate new secret key block ciphers based on the AES and Feistel ... more In this paper we study how to generate new secret key block ciphers based on the AES and Feistel constructions, that allow arbitrary large input/output lengths while maintaining the ability to select-a priori-arbitrary security levels. We start from the generation of block ciphers that are simple balanced Feistel constructions that exploit the pseudorandomness of functions, namely the AES, as round function. This results in block ciphers with inputs and outputs of size 256 bits, i.e., that are doubled compared to the AES. We then extend this principle following the "Russian Doll" design principle to build block ciphers with (arbitrarily) larger inputs and outputs. As an example, we build block ciphers with an expected security in about 2 512 , or 2 1024 , instead of 2 128 for the classical AES with 128 key-bits. The expected security is not proven, but our constructions are based on the best known attacks against Feistel networks with internal random permutations, as well as some natural security assumptions. We study two configurations of assumptions, leading to two families of simple and efficient new block ciphers, which can thus be seen as candidate schemes for higher security.

VEST hardware-dedicated stream ciphers are based on bijective non- linear parallel feedback shift... more VEST hardware-dedicated stream ciphers are based on bijective non- linear parallel feedback shift registers assisted by non-linear Remainder Number System (RNS) based counters. Three VEST cipher family trees are introduced: VEST-4, VEST-16 and VEST-32. VEST-4 returning 4 bits of output per clock cycle occupying ~4K ASIC gates offers 80-bit security, perfect for low-area low-cost applications such as RFID and smartcards. VEST-16 returning 16 bits of output per clock cycle occupying ~12K ASIC gates offers 160-bit security, perfect for high-speed low-area low cost applications. VEST-32 returning 32 bits of output per clock cycle occupying ~20K ASIC gates offers 256-bit security, perfect for high-speed high security applications such as processor-bus encryption. All VEST ciphers support variable key sizes and instant re-keying, and all VEST ciphers release output on every clock cycle.

VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST fam... more VEST is a set of four stream cipher families targeted to semiconductor applications. All VEST family members support efficient encryption, single pass authenticated encryption, and collision resistant hashing in the one low area module. VEST was submitted by Synaptic Laboratories to the ECRYPT NoE eSTREAM project in 2005. Recently, a single digit typographical error was identified in the VEST counter diffuser description 1. Shortly afterwards Antoine Joux and Jean-René Reinhard [1] published collisions in the counter-diffuser based upon the erroneous description. By extending these collisions across the entire cipher state, they were able to explore various attack scenarios. We prove that the correction of the typographical error removes all the exploitable collisions in the counter diffuser during key and IV loading operations; thereby establishing that the Joux-Reinhard attacks are an artefact of the erroneous description. Complete test vectors are included.

VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-... more VEST ciphers are based on bijective non-linear parallel feedback shift registers assisted by non-linear Residue Number System (RNS) based counters. Four VEST cipher family trees are introduced: 80-bit secure VEST-4, 128-bit secure VEST-8, 160-bit secure VEST-16 and 256-bit secure VEST-32. VEST ciphers return 4 to 32 bits of output per clock cycle while occupying ~5K to ~22K ASIC gates including

This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ... more This paper demonstrates operation of the authenticated encryption mode in VEST ciphers. All VEST ciphers operating in the authenticated encryption mode with infinite error propagation provide keyed message authentication at the same speed as their keystream generation, with negligible overhead and maintaining their security ratings.