Binjie Cheng - Academia.edu (original) (raw)

Papers by Binjie Cheng

2013 14th International Conference on Ultimate Integration on Silicon (ULIS), 2013

ABSTRACT Statistical variability and reliability is a critical issue in conventional bulk planar ... more ABSTRACT Statistical variability and reliability is a critical issue in conventional bulk planar MOSFETs of the 20 nm technology. In this paper we present a comprehensive simulation study of the impact of the drain-bias on the statistical variability in corresponding bulk MOSFETs including the threshold-voltage and the drain-induced barrier lowering (DIBL) which are two important transistor figures of merit. It was found that the threshold-voltage fluctuation increases with drain-bias but the magnitude depends on the dominant statistical variability source including random dopants (RDD), gate line edge roughness (LER), possible metal gate granularity (MGG), and random interface trapped charges (ITC). The correlations between threshold-voltage and DIBL are strongly dependent on the nature of the statistical variability source. RDD, MGG, and ITC are the major contributors to the DIBL variability.

In this paper we have studied the impact of quantum confinement on the performance of n-type sili... more In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

2014 20th International Conference on Ion Implantation Technology (IIT), 2014

ABSTRACT A simulation program, Anadope3D, developed to model ion implantations in FinFETs based o... more ABSTRACT A simulation program, Anadope3D, developed to model ion implantations in FinFETs based on quasi-analytic methods, has been improved to include a set of analytical implantation models based on a Pearson distribution function, which is concise and computationally efficient. This C++ module has been integrated into the GSS atomistic device simulator GARAND, which enables more realistic doping distributions arising from ion implantation to be used for TCAD FinFET simulations. Simulations are performed on an example of an SOI FinFET with physical gate length of 20nm, including statistical simulations with Random Discrete Dopants (RDD). The impact of the realistic 3D doping profile on FinFET performance has been investigated.

Nanostructure Science and Technology, 2007

ABSTRACT The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS)... more ABSTRACT The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS) technology to achieve faster devices and higher device density and to reduce the cost per function has fueled the phenomenal growth and success of the semiconductor industry—captured over the past 40 years by Moore’s famous law. The International Technology Roadmap for Semiconductors (ITRS) predicts, as illustrated in Table 7.1, that 7-nm physical-gate-length CMOS transistors will be in mass production in 2018. The Roadmap of the leading integrated circuit (IC) manufacturer, IBM, goes further (see Table 7.2), predicting that the physical length of the transistors will reach 3 nm by 2025. Indeed, transistors with a 45-nm channel length are in mass production now in the 90-nm technology node and functioning transistors with a 4-nm channel length have been demonstrated already by NEC at IEDM 2003. Although it is clear that the scaling of the CMOS transistors will continue in the next two decades, it is widely recognized that intrinsic parameter fluctuations introduced by the discreteness of charge and matter will be a major factor limiting the integration of such devices with molecular dimensions in giga-transistor count chips. TABLE 7.1.Extract from theInternational Technology Roadmap forSemiconductors 2003. TABLE 7.2.IBMRoadmap, Dec. 2003.

IEEE Transactions on Electron Devices, 2015

ABSTRACT In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) p... more ABSTRACT In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

2013 14th International Conference on Ultimate Integration on Silicon (ULIS), 2013

ABSTRACT The use of III–V and Ge as channel materials is a feasible alternative to Si for the nex... more ABSTRACT The use of III–V and Ge as channel materials is a feasible alternative to Si for the next generation of planar CMOS. We present a set of BSIM4 compact models for III–V and Ge Implant Free Quantum Well (IFQW) transistors which are extracted from well-calibrated TCAD simulations that include the impact of process induced statistical variability. We consider the design of 6T-SRAM using this simulation approach, and investigate the impact of process variability on the memory cell performance. The optimized cell design solutions are presented and discussed.

IEEE Transactions on Electron Devices, 2014

ABSTRACT In this paper, by means of simulation, we have studied the implications of using channel... more ABSTRACT In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping level of high-performance FinFETs designed for 100-nA/(mu )m leakage current has been increased to achieve 10 and 1-nA/(mu )m leakage currents. Ensemble Monte Carlo (EMC) simulations are used to estimate the impact of the increased doping on the transistor performance. Atomistic drift-diffusion simulations calibrated to the results of the EMC simulations are used to evaluate the impact of random discrete dopants, line edge roughness, and metal gate granularity on the statistical variability. The results of the statistical variability simulations are also used to highlight errors resulting from the use of continuous doping in the TCAD simulation of advanced CMOS technology generation FinFETs.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This paper presents a framework to investigate the potential impact of time-dependent va... more ABSTRACT This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET at 25, 18 and 13nm nodes are calibrated by a 3D atomistic device simulator with chip measurements of 35nm gate length devices. Synthesis results confirm that the variability of circuit performance will increase as device scaling continues, and can be more severe in new circuits at 18nm than in those stressed for a period of three years at 35nm. In addition, the results also reveal that increasing power consumption as adopted in adaptive supply voltage (ASV) and adaptive back bias (ABB) schemes is not a sustainable solution to compensate the drift in performance for future generations of CMOS circuits and systems.

2012 IEEE International SOI Conference (SOI), 2012

ABSTRACT Statistical variability (SV) critically affects the scaling, performance, leakage power,... more ABSTRACT Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems [1]. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), metal gate granularity (MGG) leading to work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI [2-4]. The different physical nature of these phenomena affects the spread of threshold voltage (Vth), on-current (Ion), and DIBL of the transistors in different ways, and is, for the first time, comprehensively studied here for three LOP-technology generations of n-channel UTB-FD-SOI devices with a physical gate length LG of 22, 16, and 11 nm.

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013

ABSTRACT Variability is a critical concern for the stability and yield of SRAM with minimized siz... more ABSTRACT Variability is a critical concern for the stability and yield of SRAM with minimized size. We present a study of a 14 nm node SOI FinFET SRAM cell under the influence of statistical variability and random charge trapping due to positive/negative bias temperature instability (P/NBTI). Low channel doping is believed to be one of the main advantages of FinFETs in reducing statistical variability, but fin and gate edge roughness and metal gate granularity can cause significant variability and affect SRAM stability. The noise margins are largely skewed, and read and write noise margins are decorrelated due to statistical variability. Under heavy stress conditions cell read noise margin can be degraded by 30mV on average due to charge trapping, and its 6σ-yield becomes even worse due to the enhanced variability in N/PBTI.

IEEE Custom Integrated Circuits Conference 2010, 2010

ABSTRACT Statistical variability associated with discreteness of charge and granularity of matter... more ABSTRACT Statistical variability associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. The major MOSFET statistical variability sources and corresponding physical simulations are discussed in detail. Direct statistical parameter extraction approach is presented and the scalability of 6T and 8T SRAM of bulk CMOS technology is investigated. The standard statistical parameter generation approaches are benchmarked and newly developed parameter generation approach based on nonlinear power method is outlined.

The Eighth International Conference on Advanced Semiconductor Devices and Microsystems, 2010

ABSTRACT An efficient method to accurately capture quantum confinement effects within Monte Carlo... more ABSTRACT An efficient method to accurately capture quantum confinement effects within Monte Carlo (MC) simulation while simultaneously resolving `ab initio' ionized impurity scattering via the density gradient (DG) formalism is presented. The model is applied to study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. Such simulations result in an increase in drain current variability when compared with similarly quantum corrected drift diffusion (DD) simulation. Following this, an efficient three-stage hierarchical strategy is presented that propagates the increased on-current variability captured in 3D quantum corrected `ab initio' MC into efficient 3D DD simulations that are in turn used to obtain target ID-VG characteristics for the extraction of statistical compact models.

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013

ABSTRACT We propose a way of modeling device variability in sub-threshold slope and DIBL at circu... more ABSTRACT We propose a way of modeling device variability in sub-threshold slope and DIBL at circuit-level using dependent voltage sources. The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. Benchmark experiments on circuit level, using a set of 1000 TCAD-based 10nm-FinFet device models with mismatch as a reference, show systematic accuracy improvements on mean and standard deviation of 6T-SRAM cell stability metrics of up to 30 and 10 percentage scores, respectively.

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011

As feature sizes shrink, random fluctuations gain im- portance in semiconductor manufacturing and... more As feature sizes shrink, random fluctuations gain im- portance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be consid- ered in circuit design and analysis to properly estimate their impact and avoid expensive over-design. Statistical MOSFET compact modeling is required to accurately capture marginal distributions of varying device parameters and to preserve their statistical correlations.

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012

ABSTRACT A comprehensive statistical variability simulation study of a 10nm gate length FinFET de... more ABSTRACT A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012

ABSTRACT This abstract presents a comprehensive 3D simulation study on the impact of a single int... more ABSTRACT This abstract presents a comprehensive 3D simulation study on the impact of a single interface trapped charge in emerging 20nm gate-length FinFETs on an SOI substrate. The impact of the location of trapped charges on the Random Telegraph Signal (RTS) amplitudes is studied in detail. The RTS amplitude associated with particular trap position depends on the complex current density distribution in the Fin and is modified by 'native' statistical variability sources such as metal gate granularity (MGG), line edge roughness (LER), and random discrete dopants (RDD).

2010 18th Iranian Conference on Electrical Engineering, 2010

ABSTRACT In this paper the capacitance components of the PSP compact model which is selected as s... more ABSTRACT In this paper the capacitance components of the PSP compact model which is selected as successor of BSIM4 by the Compact Modelling Council (CMC) are investigated and simulated in HSPICE for the state of the art 35nm MOSFET device. The simulations are compared with TCAD results in both transcapacitance components between the device terminals and time domain to show the impact of accuracy of compact model on real circuit simulations.

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

... F. Murray School of Engineering University of Edinburgh Edinburgh EH9 3JL, United Kingdom Ema... more ... F. Murray School of Engineering University of Edinburgh Edinburgh EH9 3JL, United Kingdom Email: {Tong-Boon.Tang,AFMurray}@ee.ed.ac ... In additional to random discrete dopants (RDD), two other sources of static statistical variability, namely line edge roughness (LER) and ...

2011 International Electron Devices Meeting, 2011

2013 14th International Conference on Ultimate Integration on Silicon (ULIS), 2013

ABSTRACT Statistical variability and reliability is a critical issue in conventional bulk planar ... more ABSTRACT Statistical variability and reliability is a critical issue in conventional bulk planar MOSFETs of the 20 nm technology. In this paper we present a comprehensive simulation study of the impact of the drain-bias on the statistical variability in corresponding bulk MOSFETs including the threshold-voltage and the drain-induced barrier lowering (DIBL) which are two important transistor figures of merit. It was found that the threshold-voltage fluctuation increases with drain-bias but the magnitude depends on the dominant statistical variability source including random dopants (RDD), gate line edge roughness (LER), possible metal gate granularity (MGG), and random interface trapped charges (ITC). The correlations between threshold-voltage and DIBL are strongly dependent on the nature of the statistical variability source. RDD, MGG, and ITC are the major contributors to the DIBL variability.

In this paper we have studied the impact of quantum confinement on the performance of n-type sili... more In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

2014 20th International Conference on Ion Implantation Technology (IIT), 2014

ABSTRACT A simulation program, Anadope3D, developed to model ion implantations in FinFETs based o... more ABSTRACT A simulation program, Anadope3D, developed to model ion implantations in FinFETs based on quasi-analytic methods, has been improved to include a set of analytical implantation models based on a Pearson distribution function, which is concise and computationally efficient. This C++ module has been integrated into the GSS atomistic device simulator GARAND, which enables more realistic doping distributions arising from ion implantation to be used for TCAD FinFET simulations. Simulations are performed on an example of an SOI FinFET with physical gate length of 20nm, including statistical simulations with Random Discrete Dopants (RDD). The impact of the realistic 3D doping profile on FinFET performance has been investigated.

Nanostructure Science and Technology, 2007

ABSTRACT The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS)... more ABSTRACT The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS) technology to achieve faster devices and higher device density and to reduce the cost per function has fueled the phenomenal growth and success of the semiconductor industry—captured over the past 40 years by Moore’s famous law. The International Technology Roadmap for Semiconductors (ITRS) predicts, as illustrated in Table 7.1, that 7-nm physical-gate-length CMOS transistors will be in mass production in 2018. The Roadmap of the leading integrated circuit (IC) manufacturer, IBM, goes further (see Table 7.2), predicting that the physical length of the transistors will reach 3 nm by 2025. Indeed, transistors with a 45-nm channel length are in mass production now in the 90-nm technology node and functioning transistors with a 4-nm channel length have been demonstrated already by NEC at IEDM 2003. Although it is clear that the scaling of the CMOS transistors will continue in the next two decades, it is widely recognized that intrinsic parameter fluctuations introduced by the discreteness of charge and matter will be a major factor limiting the integration of such devices with molecular dimensions in giga-transistor count chips. TABLE 7.1.Extract from theInternational Technology Roadmap forSemiconductors 2003. TABLE 7.2.IBMRoadmap, Dec. 2003.

IEEE Transactions on Electron Devices, 2015

ABSTRACT In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) p... more ABSTRACT In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

2013 14th International Conference on Ultimate Integration on Silicon (ULIS), 2013

ABSTRACT The use of III–V and Ge as channel materials is a feasible alternative to Si for the nex... more ABSTRACT The use of III–V and Ge as channel materials is a feasible alternative to Si for the next generation of planar CMOS. We present a set of BSIM4 compact models for III–V and Ge Implant Free Quantum Well (IFQW) transistors which are extracted from well-calibrated TCAD simulations that include the impact of process induced statistical variability. We consider the design of 6T-SRAM using this simulation approach, and investigate the impact of process variability on the memory cell performance. The optimized cell design solutions are presented and discussed.

IEEE Transactions on Electron Devices, 2014

ABSTRACT In this paper, by means of simulation, we have studied the implications of using channel... more ABSTRACT In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping level of high-performance FinFETs designed for 100-nA/(mu )m leakage current has been increased to achieve 10 and 1-nA/(mu )m leakage currents. Ensemble Monte Carlo (EMC) simulations are used to estimate the impact of the increased doping on the transistor performance. Atomistic drift-diffusion simulations calibrated to the results of the EMC simulations are used to evaluate the impact of random discrete dopants, line edge roughness, and metal gate granularity on the statistical variability. The results of the statistical variability simulations are also used to highlight errors resulting from the use of continuous doping in the TCAD simulation of advanced CMOS technology generation FinFETs.

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This paper presents a framework to investigate the potential impact of time-dependent va... more ABSTRACT This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET at 25, 18 and 13nm nodes are calibrated by a 3D atomistic device simulator with chip measurements of 35nm gate length devices. Synthesis results confirm that the variability of circuit performance will increase as device scaling continues, and can be more severe in new circuits at 18nm than in those stressed for a period of three years at 35nm. In addition, the results also reveal that increasing power consumption as adopted in adaptive supply voltage (ASV) and adaptive back bias (ABB) schemes is not a sustainable solution to compensate the drift in performance for future generations of CMOS circuits and systems.

2012 IEEE International SOI Conference (SOI), 2012

ABSTRACT Statistical variability (SV) critically affects the scaling, performance, leakage power,... more ABSTRACT Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems [1]. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), metal gate granularity (MGG) leading to work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI [2-4]. The different physical nature of these phenomena affects the spread of threshold voltage (Vth), on-current (Ion), and DIBL of the transistors in different ways, and is, for the first time, comprehensively studied here for three LOP-technology generations of n-channel UTB-FD-SOI devices with a physical gate length LG of 22, 16, and 11 nm.

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013

ABSTRACT Variability is a critical concern for the stability and yield of SRAM with minimized siz... more ABSTRACT Variability is a critical concern for the stability and yield of SRAM with minimized size. We present a study of a 14 nm node SOI FinFET SRAM cell under the influence of statistical variability and random charge trapping due to positive/negative bias temperature instability (P/NBTI). Low channel doping is believed to be one of the main advantages of FinFETs in reducing statistical variability, but fin and gate edge roughness and metal gate granularity can cause significant variability and affect SRAM stability. The noise margins are largely skewed, and read and write noise margins are decorrelated due to statistical variability. Under heavy stress conditions cell read noise margin can be degraded by 30mV on average due to charge trapping, and its 6σ-yield becomes even worse due to the enhanced variability in N/PBTI.

IEEE Custom Integrated Circuits Conference 2010, 2010

ABSTRACT Statistical variability associated with discreteness of charge and granularity of matter... more ABSTRACT Statistical variability associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. The major MOSFET statistical variability sources and corresponding physical simulations are discussed in detail. Direct statistical parameter extraction approach is presented and the scalability of 6T and 8T SRAM of bulk CMOS technology is investigated. The standard statistical parameter generation approaches are benchmarked and newly developed parameter generation approach based on nonlinear power method is outlined.

The Eighth International Conference on Advanced Semiconductor Devices and Microsystems, 2010

ABSTRACT An efficient method to accurately capture quantum confinement effects within Monte Carlo... more ABSTRACT An efficient method to accurately capture quantum confinement effects within Monte Carlo (MC) simulation while simultaneously resolving `ab initio' ionized impurity scattering via the density gradient (DG) formalism is presented. The model is applied to study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. Such simulations result in an increase in drain current variability when compared with similarly quantum corrected drift diffusion (DD) simulation. Following this, an efficient three-stage hierarchical strategy is presented that propagates the increased on-current variability captured in 3D quantum corrected `ab initio' MC into efficient 3D DD simulations that are in turn used to obtain target ID-VG characteristics for the extraction of statistical compact models.

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013

ABSTRACT We propose a way of modeling device variability in sub-threshold slope and DIBL at circu... more ABSTRACT We propose a way of modeling device variability in sub-threshold slope and DIBL at circuit-level using dependent voltage sources. The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. Benchmark experiments on circuit level, using a set of 1000 TCAD-based 10nm-FinFet device models with mismatch as a reference, show systematic accuracy improvements on mean and standard deviation of 6T-SRAM cell stability metrics of up to 30 and 10 percentage scores, respectively.

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011

As feature sizes shrink, random fluctuations gain im- portance in semiconductor manufacturing and... more As feature sizes shrink, random fluctuations gain im- portance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be consid- ered in circuit design and analysis to properly estimate their impact and avoid expensive over-design. Statistical MOSFET compact modeling is required to accurately capture marginal distributions of varying device parameters and to preserve their statistical correlations.

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012

ABSTRACT A comprehensive statistical variability simulation study of a 10nm gate length FinFET de... more ABSTRACT A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012

ABSTRACT This abstract presents a comprehensive 3D simulation study on the impact of a single int... more ABSTRACT This abstract presents a comprehensive 3D simulation study on the impact of a single interface trapped charge in emerging 20nm gate-length FinFETs on an SOI substrate. The impact of the location of trapped charges on the Random Telegraph Signal (RTS) amplitudes is studied in detail. The RTS amplitude associated with particular trap position depends on the complex current density distribution in the Fin and is modified by 'native' statistical variability sources such as metal gate granularity (MGG), line edge roughness (LER), and random discrete dopants (RDD).

2010 18th Iranian Conference on Electrical Engineering, 2010

ABSTRACT In this paper the capacitance components of the PSP compact model which is selected as s... more ABSTRACT In this paper the capacitance components of the PSP compact model which is selected as successor of BSIM4 by the Compact Modelling Council (CMC) are investigated and simulated in HSPICE for the state of the art 35nm MOSFET device. The simulations are compared with TCAD results in both transcapacitance components between the device terminals and time domain to show the impact of accuracy of compact model on real circuit simulations.

Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010

... F. Murray School of Engineering University of Edinburgh Edinburgh EH9 3JL, United Kingdom Ema... more ... F. Murray School of Engineering University of Edinburgh Edinburgh EH9 3JL, United Kingdom Email: {Tong-Boon.Tang,AFMurray}@ee.ed.ac ... In additional to random discrete dopants (RDD), two other sources of static statistical variability, namely line edge roughness (LER) and ...

2011 International Electron Devices Meeting, 2011