Bipul Paul - Academia.edu (original) (raw)
Papers by Bipul Paul
170 65.2 6.0 (Light gr.een) (65.8) (6.3) Me4N[RuCl4(Me2S0h1260(d) 20.1 5.3 2.7 1.8 (Orange yellow... more 170 65.2 6.0 (Light gr.een) (65.8) (6.3) Me4N[RuCl4(Me2S0h1260(d) 20.1 5.3 2.7 1.8 (Orange yellow) (20.3) (5.1) (2.9) Et4N[RuBr4(Me2S0hl 205-20.8 4.9 1.8 1.92 (Violet) 208 (20.4) (4.5) (2.0) fac or mer-[RuCI)(MezSOhl (0.5g) in ethanol (30 cm3), a solution of AgCI04 in ethanol {I 0 cm3) was added. The molar ratio of the complex: AgCI04 was 1:4 in the case offac-or mer-[RuCh(MezSO»)l and 1:8 in the case of [RuzCI6(MezSO)4l. The mixture was stirred at room temperature for 10-12 h and then refluxed on a water-bath for 1 hr. The solution was cooled to room temperature and the precipitated Agel was separated by centrifugation. To the light violet mother liquor, dimethyl sulphoxide (1 cm3) was added and content stirred at room temperature for 2-3 h. The solution was concentrated on a water-bath to a small volume ('" 2 mI). It was cooled in ice and methanol was added to precipitate the violet compound. The compound was recrystallized from acetone and dried in vacuo; yield 0.82g (75%).
2008 International Interconnect Technology Conference, 2008
A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and... more A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.
![Research paper thumbnail of Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]](https://attachments.academia-assets.com/116977855/thumbnails/1.jpg)
](Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in ... more In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however, for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. Design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.
Proceedings of the Design Automation & Test in Europe Conference, 2006
This paper presents a novel design methodology for ultralow power design (in bulk and double-gate... more This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5x (for bulk) and ~3.8x (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation.
Lecture Notes in Electrical Engineering, 2010
... Carbon nanotube FETs (CNFET) have been shown to have potential of taking this place in ... de... more ... Carbon nanotube FETs (CNFET) have been shown to have potential of taking this place in ... design guideline will be discussed and progresses in achieving densely packed nanotube channels (for ... needs to be significantly reduced, in order to achieve the supe-rior performance ...
2004 International Conferce on Test
A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology ... more A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [10], [11]. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dual V th technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level.
Proceedings of the Design Automation & Test in Europe Conference, 2006
Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reli... more Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.
Proceedings of the 41st annual Design Automation Conference, 2004
Due to process parameter variations, a large variability in circuit delay occurs in scaled techno... more Due to process parameter variations, a large variability in circuit delay occurs in scaled technologies affecting the yield. In this paper, we propose a sizing algorithm to ensure the speed of a circuit under process variation with a certain degree of confidence while maintaining the area and power budget within a limit. This algorithm estimates the variation in circuit delay using statistical timing analysis considering both interand intra-die process variation and resizes the circuit to achieve a desired yield. Experimental results on several benchmark circuits show that one can achieve up to 19% savings in area (power) using our algorithm compared to the worst-case design.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single ... more We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single substrate suitable for emerging hybrid nanotechnology applications. This co-integration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal processing of sensor output. We demonstrate the
2009 IEEE International Electron Devices Meeting (IEDM 2009), 2009
We have successfully experimentally integrated graphene interconnects with commercial 0.25μm tech... more We have successfully experimentally integrated graphene interconnects with commercial 0.25μm technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1GHz.
Low-Power Variation-Tolerant Design in Nanometer Silicon, 2010
... Apart from the alternative bitcell architectures, array level techniques to facilitate read a... more ... Apart from the alternative bitcell architectures, array level techniques to facilitate read and/or write, as ... 6.15 Measured data from the schmitt trigger SRAM cell illustrates better voltage scalability [33, 34] Fig ... IEEE Trans VLSI Syst 9 (1): 9099 4. Wang A, Chandrakasan A (Jan 2005 ...
2006 64th Device Research Conference, 2006
This paper provides a guideline to optimize the oxide thickness of bulk MOSFET for digital sub-th... more This paper provides a guideline to optimize the oxide thickness of bulk MOSFET for digital sub-threshold operation. We show that minimum possible oxide thickness provided by the technology may not always result in minimum energy for digital sub-threshold operation. The optimum oxide thickness is also shown to be less sensitive to process variation.
Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00, 2000
25th IEEE VLSI Test Symmposium (VTS'07), 2007
Circuit failure prediction predicts the occurrence of a circuit failure before errors actually ap... more Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. In a recent paper [Agarwal 07], we demonstrated this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by Negative Bias Temperature Instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worstcase speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a very low cost. Actual test chip prototype demonstrates correct operations of such flip-flops with built-in aging sensors. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.
Nano Letters, 2008
Due to their excellent electrical properties, metallic carbon nanotubes are promising materials f... more Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
This paper presents a novel design methodology for ultralow-power design using subthreshold leaka... more This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for superthreshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows 2.5 improvement in throughput at iso-power compared to a conventional design.
IEEE Transactions on Nanotechnology, 2008
... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applicat... more ... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complexCMOS electronics for sensor control, calibration, and signal pro-cessing. ...
IEEE Transactions on Electron Devices, 2007
In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and driftdiffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.
170 65.2 6.0 (Light gr.een) (65.8) (6.3) Me4N[RuCl4(Me2S0h1260(d) 20.1 5.3 2.7 1.8 (Orange yellow... more 170 65.2 6.0 (Light gr.een) (65.8) (6.3) Me4N[RuCl4(Me2S0h1260(d) 20.1 5.3 2.7 1.8 (Orange yellow) (20.3) (5.1) (2.9) Et4N[RuBr4(Me2S0hl 205-20.8 4.9 1.8 1.92 (Violet) 208 (20.4) (4.5) (2.0) fac or mer-[RuCI)(MezSOhl (0.5g) in ethanol (30 cm3), a solution of AgCI04 in ethanol {I 0 cm3) was added. The molar ratio of the complex: AgCI04 was 1:4 in the case offac-or mer-[RuCh(MezSO»)l and 1:8 in the case of [RuzCI6(MezSO)4l. The mixture was stirred at room temperature for 10-12 h and then refluxed on a water-bath for 1 hr. The solution was cooled to room temperature and the precipitated Agel was separated by centrifugation. To the light violet mother liquor, dimethyl sulphoxide (1 cm3) was added and content stirred at room temperature for 2-3 h. The solution was concentrated on a water-bath to a small volume ('" 2 mI). It was cooled in ice and methanol was added to precipitate the violet compound. The compound was recrystallized from acetone and dried in vacuo; yield 0.82g (75%).
2008 International Interconnect Technology Conference, 2008
A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and... more A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in ... more In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however, for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. Design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.
Proceedings of the Design Automation & Test in Europe Conference, 2006
This paper presents a novel design methodology for ultralow power design (in bulk and double-gate... more This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5x (for bulk) and ~3.8x (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation.
Lecture Notes in Electrical Engineering, 2010
... Carbon nanotube FETs (CNFET) have been shown to have potential of taking this place in ... de... more ... Carbon nanotube FETs (CNFET) have been shown to have potential of taking this place in ... design guideline will be discussed and progresses in achieving densely packed nanotube channels (for ... needs to be significantly reduced, in order to achieve the supe-rior performance ...
2004 International Conferce on Test
A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology ... more A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [10], [11]. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dual V th technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level.
Proceedings of the Design Automation & Test in Europe Conference, 2006
Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reli... more Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.
Proceedings of the 41st annual Design Automation Conference, 2004
Due to process parameter variations, a large variability in circuit delay occurs in scaled techno... more Due to process parameter variations, a large variability in circuit delay occurs in scaled technologies affecting the yield. In this paper, we propose a sizing algorithm to ensure the speed of a circuit under process variation with a certain degree of confidence while maintaining the area and power budget within a limit. This algorithm estimates the variation in circuit delay using statistical timing analysis considering both interand intra-die process variation and resizes the circuit to achieve a desired yield. Experimental results on several benchmark circuits show that one can achieve up to 19% savings in area (power) using our algorithm compared to the worst-case design.
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single ... more We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single substrate suitable for emerging hybrid nanotechnology applications. This co-integration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal processing of sensor output. We demonstrate the
2009 IEEE International Electron Devices Meeting (IEDM 2009), 2009
We have successfully experimentally integrated graphene interconnects with commercial 0.25μm tech... more We have successfully experimentally integrated graphene interconnects with commercial 0.25μm technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1GHz.
Low-Power Variation-Tolerant Design in Nanometer Silicon, 2010
... Apart from the alternative bitcell architectures, array level techniques to facilitate read a... more ... Apart from the alternative bitcell architectures, array level techniques to facilitate read and/or write, as ... 6.15 Measured data from the schmitt trigger SRAM cell illustrates better voltage scalability [33, 34] Fig ... IEEE Trans VLSI Syst 9 (1): 9099 4. Wang A, Chandrakasan A (Jan 2005 ...
2006 64th Device Research Conference, 2006
This paper provides a guideline to optimize the oxide thickness of bulk MOSFET for digital sub-th... more This paper provides a guideline to optimize the oxide thickness of bulk MOSFET for digital sub-threshold operation. We show that minimum possible oxide thickness provided by the technology may not always result in minimum energy for digital sub-threshold operation. The optimum oxide thickness is also shown to be less sensitive to process variation.
Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00, 2000
25th IEEE VLSI Test Symmposium (VTS'07), 2007
Circuit failure prediction predicts the occurrence of a circuit failure before errors actually ap... more Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. In a recent paper [Agarwal 07], we demonstrated this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by Negative Bias Temperature Instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worstcase speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a very low cost. Actual test chip prototype demonstrates correct operations of such flip-flops with built-in aging sensors. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.
Nano Letters, 2008
Due to their excellent electrical properties, metallic carbon nanotubes are promising materials f... more Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
This paper presents a novel design methodology for ultralow-power design using subthreshold leaka... more This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for superthreshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows 2.5 improvement in throughput at iso-power compared to a conventional design.
IEEE Transactions on Nanotechnology, 2008
... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applicat... more ... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complexCMOS electronics for sensor control, calibration, and signal pro-cessing. ...
IEEE Transactions on Electron Devices, 2007
In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and driftdiffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.