Bipul Paul - Academia.edu (original) (raw)

Papers by Bipul Paul

Research paper thumbnail of A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport

In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and drift-diffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for I-V and C-V characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of a NWFET device. Results show a close match of the model with measured data.

Research paper thumbnail of Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit

2008 International Interconnect Technology Conference, 2008

A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and... more A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.

Research paper thumbnail of Modeling and analysis of circuit performance of ballistic CNFET

Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006

With the advent of carbon nanotube technology, evaluating circuit and system performance using th... more With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasianalytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-ofthe-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Research paper thumbnail of Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications

ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008

We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single ... more We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single substrate suitable for emerging hybrid nanotechnology applications. This co-integration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal processing of sensor output. We demonstrate the

Research paper thumbnail of High-Speed Graphene Interconnects Monolithically Integrated with CMOS Ring Oscillators Operating at 1.3 GHz

2009 IEEE International Electron Devices Meeting (IEDM 2009), 2009

We have successfully experimentally integrated graphene interconnects with commercial 0.25μm tech... more We have successfully experimentally integrated graphene interconnects with commercial 0.25μm technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1GHz.

Research paper thumbnail of Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface

Physical Review B, 2010

Organic or carbon semiconductor devices are promising for both nanoelectronic and macroelectronic... more Organic or carbon semiconductor devices are promising for both nanoelectronic and macroelectronic applications. One of the major challenges to achieve high performance of these devices lies on understanding and improving the metal-organic ͑M/O͒ interface. In this paper, we present evidence and demonstration of Fermilevel depinning at the M/O interface by inserting an ultrathin interfacial Si 3 N 4 insulator in between. The M/O contact behavior is successfully tuned from rectifying to quasi-Ohmic and to tunneling by varying the Si 3 N 4 thickness within 0-6 nm. Detailed physical mechanisms of Fermi-level pinning/depinning responsible for the M/O contact behavior are clarified based on a lumped-dipole model and a simple depinning model. This work sheds light on the fundamental understanding of the M/O interface properties and also proves a practical engineering method of achieving low-resistance quasi-Ohmic contacts for organic electronic devices.

Research paper thumbnail of A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors

Nano Letters, 2008

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials f... more Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Research paper thumbnail of Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications

IEEE Transactions on Nanotechnology, 2008

... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applicat... more ... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complexCMOS electronics for sensor control, calibration, and signal pro-cessing. ...

Research paper thumbnail of An Analytical Compact Circuit Model for Nanowire FET

IEEE Transactions on Electron Devices, 2007

In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and driftdiffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.

Research paper thumbnail of Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

IEEE Transactions on Electron Devices, 2010

Carbon-based nanomaterials such as metallic singlewalled carbon nanotubes, multiwalled carbon nan... more Carbon-based nanomaterials such as metallic singlewalled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal-oxide-semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%.

Research paper thumbnail of Prospect of ballistic CNFET in high performance applications

ACM Journal on Emerging Technologies in Computing Systems, 2007

With the advent of carbon nanotube technology, evaluating circuit and system performance using th... more With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sens...

Research paper thumbnail of Impact of a Process Variation on Nanowire and Nanotube Device Performance

IEEE Transactions on Electron Devices, 2007

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance un... more In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications.

Research paper thumbnail of A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport

In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and drift-diffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for I-V and C-V characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of a NWFET device. Results show a close match of the model with measured data.

Research paper thumbnail of Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit

2008 International Interconnect Technology Conference, 2008

A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and... more A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.

Research paper thumbnail of Modeling and analysis of circuit performance of ballistic CNFET

Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006

With the advent of carbon nanotube technology, evaluating circuit and system performance using th... more With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasianalytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-ofthe-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Research paper thumbnail of Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications

ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008

We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single ... more We integrate carbon nanotube (CNT) fabrication with commercial CMOS VLSI fabrication on a single substrate suitable for emerging hybrid nanotechnology applications. This co-integration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complex CMOS electronics for sensor control, calibration, and signal processing of sensor output. We demonstrate the

Research paper thumbnail of High-Speed Graphene Interconnects Monolithically Integrated with CMOS Ring Oscillators Operating at 1.3 GHz

2009 IEEE International Electron Devices Meeting (IEDM 2009), 2009

We have successfully experimentally integrated graphene interconnects with commercial 0.25μm tech... more We have successfully experimentally integrated graphene interconnects with commercial 0.25μm technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene interconnects that operates above 1GHz.

Research paper thumbnail of Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface

Physical Review B, 2010

Organic or carbon semiconductor devices are promising for both nanoelectronic and macroelectronic... more Organic or carbon semiconductor devices are promising for both nanoelectronic and macroelectronic applications. One of the major challenges to achieve high performance of these devices lies on understanding and improving the metal-organic ͑M/O͒ interface. In this paper, we present evidence and demonstration of Fermilevel depinning at the M/O interface by inserting an ultrathin interfacial Si 3 N 4 insulator in between. The M/O contact behavior is successfully tuned from rectifying to quasi-Ohmic and to tunneling by varying the Si 3 N 4 thickness within 0-6 nm. Detailed physical mechanisms of Fermi-level pinning/depinning responsible for the M/O contact behavior are clarified based on a lumped-dipole model and a simple depinning model. This work sheds light on the fundamental understanding of the M/O interface properties and also proves a practical engineering method of achieving low-resistance quasi-Ohmic contacts for organic electronic devices.

Research paper thumbnail of A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors

Nano Letters, 2008

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials f... more Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Research paper thumbnail of Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications

IEEE Transactions on Nanotechnology, 2008

... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applicat... more ... This cointegration combines the inherent advantages of CMOS and CNTs. These emerging applications include CNT optical, biological, chemical, and gas sensors that require complexCMOS electronics for sensor control, calibration, and signal pro-cessing. ...

Research paper thumbnail of An Analytical Compact Circuit Model for Nanowire FET

IEEE Transactions on Electron Devices, 2007

In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballis... more In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and driftdiffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.

Research paper thumbnail of Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

IEEE Transactions on Electron Devices, 2010

Carbon-based nanomaterials such as metallic singlewalled carbon nanotubes, multiwalled carbon nan... more Carbon-based nanomaterials such as metallic singlewalled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal-oxide-semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%.

Research paper thumbnail of Prospect of ballistic CNFET in high performance applications

ACM Journal on Emerging Technologies in Computing Systems, 2007

With the advent of carbon nanotube technology, evaluating circuit and system performance using th... more With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sens...

Research paper thumbnail of Impact of a Process Variation on Nanowire and Nanotube Device Performance

IEEE Transactions on Electron Devices, 2007

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance un... more In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications.