Biswajit Mishra - Academia.edu (original) (raw)

Papers by Biswajit Mishra

Lecture Notes in Electrical Engineering, 2021

This paper proposes a Raspberry Pi (R-Pi) based system to automatically detect and classify most ... more This paper proposes a Raspberry Pi (R-Pi) based system to automatically detect and classify most of the atrial and ventricular cardiac diseases. The system provides a necessary solution for resource constrained regions to timely detect fatal cardiac conditions. The R-Pi receives the user specific information from the ECG application specifically developed for the smart mobile phones and 2-Lead ECG data from the ECG sensors connected with limb electrodes and the Arduino Nano board. The ECG data along with the user specific information is further processed for lead separation, ECG feature extraction, and disease classification. The obtained results are sent to the doctor via email. Along with the system development, this work proposes various algorithms for feature points detection and disease classifications.

IEEE Access, 2021

Over the years, researchers have studied the evolution of Electrocardiogram (ECG) and the complex... more Over the years, researchers have studied the evolution of Electrocardiogram (ECG) and the complex classification of cardiovascular diseases. This review focuses on the evolution of the ECG and covers the most recent signal processing schemes with milestones over the last 150 years systematically. Development phases of ECG, ECG leads, portable ECG monitors, Signal Processing schemes and Complex Transformations are discussed. This paper summarizes the development of ECG features detection for cardiac anomalies and the history of the development of ECG monitors, beginning from String Galvanometer. It also discusses the automated detections on ECG, beginning from 1960 to the most recent signal processing techniques. Additionally, this paper provides recommendations for future research directions.

SN Applied Sciences, 2020

The worldwide, particulate matter pollution is considered one of the deadliest types of air pollu... more The worldwide, particulate matter pollution is considered one of the deadliest types of air pollution due to its significant impact on the global environment and human health. The particulate matter (PM2.5) plays a key role in evaluating the air quality index. However, the conventional PM2.5 monitoring instruments used by the air quality monitoring stations are costly, bulkier, time-consuming, and power-hungry. Furthermore, due to limited data availability and non-scalability, it is challenging to provide high spatial and temporal resolution in real-time. To overcome these challenges, we present analytical equations based prediction approach for PM2.5 using an artificial neural network. Moreover, we contribute the correlation study between PM2.5 and other pollutants using a large authenticate data set of Central Pollution Control Board online station, India. The correlation study reveals the strong correlation of eight pollutants with PM2.5, which found useful for the proposed prediction model and future research work. The computation of the proposed analytical equation using a low-cost processing tool (excel sheet) demonstrates a good match between predicted and actual results. Additionally, the derived analytical equation for the prediction can be computed using a wireless sensor node which ultimately eliminates the need for costly propriety tools. The performance of proposed analytical equation for prediction show root mean square error and coefficient of determination (R 2) 1.80 μg/m 3 and 0.99 respectively using eight correlated predictors. The recalibrated prediction model with three correlated predictors show RMSE of 7.54 μg/m 3 and R 2 of 0.97 and proves the effectiveness of the proposed approach in implementation using minimum power-hungry gas sensors on the WSN. Therefore, obtained results demonstrate that the proposed approach is one of the promising approaches for monitoring PM2.5 without power-hungry gas sensors and bulkier analyzers.

IET Computers & Digital Techniques, 2018

In this study, the authors present a configurable architecture having gate count of ≃ 3.2k and on... more In this study, the authors present a configurable architecture having gate count of ≃ 3.2k and on the fly reconfigurability for low-power biomedical applications such as QRS detection, ExG processing etc. The proposed architecture is a lightweight co-processor that supports on-node digital signal and image processing functions potentially eliminating the power consumed by radios in wireless sensor node and body sensor network. The architecture consists of a 3 × 3 array of register units along with adaptive memory with configurable data path. The architecture can be configured on-the-fly for seven functions with the current memory structure. However, more number of functions can be targeted with increased memory. They demonstrate the realisation of Pan-Tompkins algorithm commonly used for QRS detection on the proposed architecture using the reconfigurability. This work offers ≈ 4 × reduced area and 2.3 × increase in performance with respect to the existing contemporary literature.

Sciprints, 2016

This paper investigates an Energy Neutral System using Micro Energy Harvesters for a Health Monit... more This paper investigates an Energy Neutral System using Micro Energy Harvesters for a Health Monitoring Wireless Sensor Node (HM-WSN). We have implemented HM-WSN consisting of a solar cell energy harvester, a Power Management Unit (PMU) and the ucontroller, sensor and transmitter acting as load. A battery extender and a switching logic circuit for sensor node is designed to evaluate the efficiency of the proposed system. The HM-WSN senses body temperature with improvement in lifetime of coincell. The HM-WSN is built using commercially available off the shelf (COTS components and consumes 47.2uW for data being updated every 134s. It can be operated for approximately 1.32 years only on a coincell. Furthermore, the HM-WSN can be operated with solar energy at 200lux, achieving 96.36 years with a combination of a coincell with an additional capacitor of 2.2mF. It attains 4.07 years to 16.87 years lifetime with the load capacitor varying from 1mF to 1.5mF at 350lux lighting condition. With...

Procedia Technology, 2016

In this paper we present a customized Internet of Things (IoT) enabled Wireless Sensing and Monit... more In this paper we present a customized Internet of Things (IoT) enabled Wireless Sensing and Monitoring Platform to monitor the temperature, relative humidity and light in the context of building automation. In developed system, data is sent from the transmitter node to the receiver node through a customized hopping method. The data received at the receiver node is monitored and recorded in an excel sheet in a personal computer (PC) through a Graphical User Interface (GUI), made in LabVIEW. An Android application has also been developed through which data is transferred from LabVIEW to a smartphone through which data is remotely monitored.

2015 19th International Symposium on VLSI Design and Test, 2015

The CORDIC (COrdinated Rotation DIgital Computer)[1] algorithm provides an efficient and accurate... more The CORDIC (COrdinated Rotation DIgital Computer)[1] algorithm provides an efficient and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. This paper presents the implementation of CORDIC algorithm on a configurable architecture to port various transforms which forms the heart of image and signal processing applications. We shall demonstrate this through the mapping of trigonometric, hyperbolic, logarithm and exponential CORDIC functions on the proposed architecture. Furthermore, we show the benefits of the architecture in terms of configurability and cycle timing with a reduced gate count implementation.

2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015

This paper proposes a novel reconfigurable multiplierless architecture that could be operated as ... more This paper proposes a novel reconfigurable multiplierless architecture that could be operated as a convolver, FIR filter, adder, multiplier and running average computing unit. The proposed multiplierless architecture uses only shift-and-accumulation resulting in significant saving in the gate-count making it suitable for low power applications as required in wireless sensor networks(WSN), body sensor networks(BSN).

2014 9th International Conference on Industrial and Information Systems (ICIIS), 2014

Ultra-Wide Band (UWB) technology has recently become a viable option for wireless applications th... more Ultra-Wide Band (UWB) technology has recently become a viable option for wireless applications that require high data-rate and ultra low power demand. This paper presents an all-digital UWB transmitter architecture using 0.18μm CMOS. It employs a delay line based architecture that works with Pulse Positioning Modulation (PPM), On Off Keying (OOK) and Delay Based Binary Phase Shift Keying (DB-BPSK) modulation schemes at two center frequencies (3.75GHz and 4.25GHz) with a fixed bandwidth (500MHz). The proposed transmitter generates a 2ns wide, 120mV peak to peak UWB pulse that satisfies FCC indoor Power Spectral Density requirements and consumes I6.99pJ/pulse that is comparable to state of the art implementations.

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

Abstract Subthreshold logic can dramatically reduce energy consumption, if the increased circuit ... more Abstract Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V dd &# 60; V th), one of the important consideration is to improve the ...

2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015

This paper presents a fully-digital ultra low power capacitive sensor interface, which directly c... more This paper presents a fully-digital ultra low power capacitive sensor interface, which directly converts sensor capacitance to its digital value. Capacitive sensor interface is divided into two parts, 1) Capacitance to time converter (CTC) and 2) time to digital converter (TDC). The proposed design demonstrates the working principle of CTC and TDC and its implementation using UMC 0.18 μm CMOS technology. Demonstration of CTC through capacitive controlled oscillator (CCO) is carried out by keeping sensor capacitance in the range of 5pF - 25pF. CCO generates pulse signals according to sensor capacitance and feeds it to the TDC. TDC consists of a delay line, edge combiner and counter and measures pulse width of pulse signals generated from CCO and gives their digital equivalent value in two forms:- fine timing data and coarse timing data. Finally, control logic unit is implemented to control each unit and to reduce power consumption of TDC design. The power consumption of the proposed interface is 12nW, acquisition time 528 μS, peak FOM of 47 fJ/conv with 6.1 ENOB at an operating voltage of 0.3V.

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013

ABSTRACT

The widespread use of Computer Graphics and Computer Vision applications has led to a plethora of... more The widespread use of Computer Graphics and Computer Vision applications has led to a plethora of hardware implementations that are usually expressed using linear algebraic methods. There are two drawbacks with this approach that are posing fundamental challenges to ...

Mishra, B. and Wilson, P. (2005) VLSI Implementation of a Geometric Algebra Micro Architecture. I... more Mishra, B. and Wilson, P. (2005) VLSI Implementation of a Geometric Algebra Micro Architecture. In: PREP 2005, Mar 30 - Apr 01, Lancaster, UK. pp. 50-51.Full text not available from this repository. ... EPrints is free software developed by the University of ...

Mishra, B. and Wilson, P. (2005) Hardware Implementation Of a Geometric Algebra Processor Core. I... more Mishra, B. and Wilson, P. (2005) Hardware Implementation Of a Geometric Algebra Processor Core. In: IMACS International Conference on Applications of Computer Algebra, July 31 - August 3, 2005, Nara, Japan.Full text not available from this repository. ... EPrints is free software ...