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Papers by Bulent Dervisoglu

Proceedings. International Test Conference 1990

The architecture and some of the specific features of a scan-and-clock resource (SCR) chip are de... more The architecture and some of the specific features of a scan-and-clock resource (SCR) chip are described. This chip is used in a high-end workstation product to provide access to the testability features of the individual chips and or printed circuit boards. The chip is designed to be included on each system board and is capable of controlling up to eight independent scan ports. By careful examination of different scan styles, it was discovered that there are two basic styles of scan, differentiated by their clocking mechanisms. The SCR chip uses a mode bit to specify the scan style for each port separately and by so doing to convert from the actual scan style to an internal style so that actual chip characteristics are hidden from the scan/diagnostics software. It is pointed out that using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) are emerging as a common strategy for designing testable digital systems. On the basis of experience gained from such an application, controller features which are deemed useful are discussed.<<ETX>>

International Test Conference, Oct 16, 1984

IEEE Transactions on Computers, 1981

C. V. Ramamoorthy (M'57-SM'76-F'78) received the undergraduate degrees in physics and technology ... more C. V. Ramamoorthy (M'57-SM'76-F'78) received the undergraduate degrees in physics and technology from the University of Madras, Madras, India, the M.S. degree and the professional degree of Mechanical Engineer, both from the

Techni4ue Computer Aided Design techniques are essential for the development of complex digital s... more Techni4ue Computer Aided Design techniques are essential for the development of complex digital systems. The existing methods of CAD approach the problem in two ways. The first one is to use a formal language to describe system behaviour and then use special algorithms to turn it into hardware. The second approach is to use flow-charts to specify the flow of information within a digital system and then to realise the flow-chart in hardware. A different approach is presented in this thesis. Components are described (or provided by the design system) which realise the required operations. These are displayed on a graphics screen and connections are made by drawing lines between their terminals. A simulator is used to test the design. To illustrate the use of the CAD system, a simple computer was designed. Methods for realising the idealised components in practical versions are also discussed. Part of this involves the well-known state assignment problem in sequential circuit synthesis, and a new method is presented. Use other side if necessary.

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

This paper proposes a framework to help designers understand how to integrate customized design f... more This paper proposes a framework to help designers understand how to integrate customized design for test features under the guidelines of the 1149.1 standard. The paper begins by discussing the reasoning behind some of the essential features of the IEEE 1149.1 boundary scan standard. Following that, arguments are made for allowing greater flexibility within the standard in order to accommodate

1991, Proceedings. International Test Conference

... indeed, if certain signal changes occur much faster than expected this might create hold-time... more ... indeed, if certain signal changes occur much faster than expected this might create hold-time violations which ... First, internal clock delay and skew as well as the flip-flop set-up times are ... which has been implemented on the IC component to enable its internal flip-flops to operate. ...

IEEE Design & Test of Computers, 1992

Working Group is developing a standard that supports boundary scan for board-level interconnect t... more Working Group is developing a standard that supports boundary scan for board-level interconnect testing and supports intemal Scan for device or board-level component testing. The group's overall objective is to establish minimal mandatory features that are adaptable to individual applications. This report describes P1149.2'~ current status and the most recent proposals being considered for the standard. I caution the reader that none of the following is in final form; it is all subject to change. In

Computer, 1974

The use of hardware description languages in British industries and universities is presented her... more The use of hardware description languages in British industries and universities is presented here, including both linguistic and graphical forms of representation.

Computer-Aided Design, 1975

This paper discusses some of the critical issues that may prevent IEEE P1500 from becoming an acc... more This paper discusses some of the critical issues that may prevent IEEE P1500 from becoming an acceptable standard and offers some suggestions for their solution. In particular, the inadequacy of the proposed P1500 and the VSIA solutions in handling hierarchical implementations is addressed. Support for hierarchical implementations is seen as an essential feature in a test access methodology that is intended for use in System on a Chip (SoC) designs. The author is actively pursuing some of these solutions through the working groups.

? The design cycle can be broken into the “Design Creation” (or logic design) phase followed by t... more ? The design cycle can be broken into the “Design Creation” (or logic design) phase followed by the “Design Implementation” (or physical design) phase. Logic synthesis is used to provide a mapping of the existing design description from a higher level of abstraction onto a lower level. ? DFT is inserted into a circuit by making structural changes to it. For example, scan and BIST are added by inserting special cells/circuits to enable the desired behavior during test. Since DFT is achieved via additions to the circuit description, DFT is considered as a part of Design Creation. ? The entire design (mission logic plus DFT circuits) can be processed by EDA software to transform the gatelevel descriptions into a physical implementation (i.e. placement and routing), usually represented in the form of a GDS II tape.

Cad, 1974

Presentation of a computer program for the five different cases of hinge pattern under two ultima... more Presentation of a computer program for the five different cases of hinge pattern under two ultimate loading conditions. A modified simplified limit method by Baker is proposed. Nielson, R. and Orang, P.Y. 74.18 'Structural analysis of longitudinally framed ships', Ship Structure Committee, Coastguard HQ, Washington DC, USA (1972) 60pp N-00024-70-C-5219 The method combines the advantages of the finite element technique and uncoupling by coordinate transformation. A fine mesh can be used to produce more accurate boundary conditions. The transformations also reduce the computer time to about onetenth of that by other methods. Three computer programs are discussed: one for longitudinal strength analysis, one for transverse strength analysis and a third for the local stability check of the structure.