Munkang Choi - Academia.edu (original) (raw)

Papers by Munkang Choi

Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

2006 16th Biennial University/Government/Industry Microelectronics Symposium, 2006

ABSTRACT Tensile and compressive stressed nitride liners have been used to increase the carrier m... more ABSTRACT Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout.

Analysis of microbump induced stress effects in 3D stacked IC technologies

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012

ABSTRACT Besides the stress around Cu TSV's, also the stress induced by microbumps is a m... more ABSTRACT Besides the stress around Cu TSV's, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Material Engineering for 7nm FinFETs

ECS Transactions

Design rules and several candidate channel materials are explored for the 7nm technology node. Fi... more Design rules and several candidate channel materials are explored for the 7nm technology node. FinFET transistor architecture is chosen, and the analysis is performed using 3D modeling tools, including ballistic transport, Schrodinger-driven quantization, and band-to-band tunneling leakage. The comparative analysis of Si, SiGe, Ge, GaAs, InGaAs, and InAs channel materials points to InGaAs with more than 80% Ga content as the best candidate for low power applications at 7nm design rules.

Simulation of the circuit performance impact of lithography in nanoscale semiconductor manufacturing

With nanoscale semiconductor technology, circuit performance is increasingly influenced by detail... more With nanoscale semiconductor technology, circuit performance is increasingly influenced by details of the manufacturing process. An increasing number of manufacturing features, which are not included in standard design tools, affect both circuit performance and yield. One source of circuit performance degradation is lithography imperfections. Therefore, we need to simulate how lithography imperfections impact circuit performance. Such imperfections include the proximity effect, lens aberrations, and flare. These imperfections in lithography impact circuit timing. This paper introduces a method to incorporate the proximity effect, lens aberrations, and flare in timing simulation. Our method involves expanding and revising the cell library by considering optical effects. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.

2012 International Silicon-Germanium Technology and Device Meeting (ISTDM), 2012

The SiGe source/drain is going to be the main stress source for the 14 nm PMOS FinFET due to the ... more The SiGe source/drain is going to be the main stress source for the 14 nm PMOS FinFET due to the tight gate pitch and due to the gate-last high-k metal gate (HKMG). illustrates creation of the epitaxial SiGe source/drain. On the left, the FinFET is shown before growing the SiGe. From left to right, evolution of the epitaxial SiGe shape is depicted as calculated by lattice kinetic Monte Carlo (LKMC) method. The LKMC is instrumental in exploring the epitaxial shapes for different fin geometries and crystal orientations. The rightmost image on shows the final shape of epitaxial SiGe source/drain for the standard (100) wafer with <110> aligned FinFETs. There are six {111} facets with 55 o slope.

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

2013 IEEE International Electron Devices Meeting, 2013

This work provides for the first time comprehensive and early guidelines for TSV integration in 1... more This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area. : The 10nm node CMOS technology 3D IC integration. X-section cartoon of Via-middle 3μm diameter TSV integration with 10nm Bulk FinFET.

High speed phase detector design

2003 46th Midwest Symposium on Circuits and Systems, 2003

Abstract - Twophase detector (PD) designs for phase-locked loops (PLLs) and delay-locked loops (D... more Abstract - Twophase detector (PD) designs for phase-locked loops (PLLs) and delay-locked loops (DLLs) are proposed in this paper. The first one is a high speed dynamic PD and the second one is a combined PD and charge pump (CP) circuit. The two PDs are designed with 0.18 ...

Effectiveness of strained-Si technology for thin-body MOSFETs

2012 IEEE International SOI Conference (SOI), 2012

ABSTRACT Strain-induced mobility enhancement in thin-body MOSFETs is studied and the impact of si... more ABSTRACT Strain-induced mobility enhancement in thin-body MOSFETs is studied and the impact of silicon body thickness scaling on piezoresistance coefficients is analyzed to facilitate stress engineering for these advanced transistor structures. Various stressors are benchmarked in terms of their effectiveness to enhance nanometer-gate-length thin-body MOSFET performance.

Design for Manufacturability through Design-Process Integration III, 2009

Rigorous 3D process and device simulation has been applied to transistors with curved channel sha... more Rigorous 3D process and device simulation has been applied to transistors with curved channel shapes that are inevitable due to the optical proximity effects. The impact of channel curvature on the transistor performance has been benchmarked using the universal Ion/Ioff coordinates. Systematic study of the different non-rectangular channel shapes included straight lines at an angle different than 90 degrees and concave and convex shapes with different curvature radii. The study reveals that any deviation from the ideal rectangular shape affects transistor performance. The amount of enhancement or degradation depends on particular shape, with on current, threshold voltage, and off current responding very differently to the same shape variation. The type and amount of performance variation is very different for the distorted channel length (i.e. poly gate shape) vs distorted channel width (i.e. active layer shape). Degradation of over 50% in the on current at a fixed off current has been observed in the most unfavorable cases for each of the two critical mask layers. On the other hand, a desirable over 3x off current reduction at a fixed on current can be achieved by selecting a beneficial channel shape.

Simulation of Semiconductor Processes and Devices 2004, 2004

As the critical dimension (CD) is scaled into nanometer dimensions, operating frequencies exceed ... more As the critical dimension (CD) is scaled into nanometer dimensions, operating frequencies exceed a gigahertz, and more functional blocks are added into systems on chip (SoC), interconnect has become a bottleneck in achieving the system performance [1]. In addition, scaling increases the impact of systematic intra-die CD variation (gate and metal linewidth variations) and this variation interacts with the circuit design by degrading circuit speed [2]. One major source of CD variation is the optical lithography process . To determine how the lithography variation impacts circuit performance, this paper introduces a method to incorporate the lithographycaused interconnect linewidth variation in timing simulation. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.

MRS Proceedings, 2008

The bulk CMOS devices continue to be the dominant player for the next few technology nodes. This ... more The bulk CMOS devices continue to be the dominant player for the next few technology nodes. This drives the increasingly contradicting requirements for the channel, source/drain extension, and heavily doped source/drain doping profiles. To analyze and optimize the transistors, it has become necessary to simultaneously analyze effects that have been previously decoupled. The temperature gradients, combined with stress engineering techniques such as embedded SiGe and Si:C source/drain and stress memorization techniques, create non-uniform stress distributions which are determined by the layout patterns. The interaction of implantinduced damage with dopants, stress, and defect traps defines the dopant activation, retention of useful stress, and junction leakage. This work reviews recent trends in modeling these effects using continuum and kinetic Monte Carlo methods.

Microelectronics Reliability, 2005

Two models for the effect of area scaling on reliability are derived from two distinct yield mode... more Two models for the effect of area scaling on reliability are derived from two distinct yield models with different assumptions on defect distributions. One is derived from the Poisson yield model assuming a uniform random distribution of defects as in an early model. The other is based on the negative binomial yield model to account for deviation from a uniform random distribution of defects caused by clustering. Experimental data from backend test structures show that the model based on defect clustering explains observed data well while the model assuming a uniform random distribution shows a significant departure from it.

2012 International Electron Devices Meeting, 2012

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

2010 International Electron Devices Meeting, 2010

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to ... more As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time

Exploring doping options and variability of trigate transistors using atomistic process and device simulations

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2010

Effectiveness of Stressors in Aggressively Scaled FinFETs

IEEE Transactions on Electron Devices, 2000

ABSTRACT The stress transfer efficiency (STE) and impact of process-induced stress on carrier mob... more ABSTRACT The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggressively scaled FinFETs are studied for different stressor technologies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is $ \hbox{1.5}\times$ larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the channel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected.

Diagnosis of Optical Lithography Faults With Product Test Sets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

ABSTRACT Increasing within-die variation, combined with larger numbers of critical and near-criti... more ABSTRACT Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits.