Christian Raya - Academia.edu (original) (raw)

Papers by Christian Raya

Research paper thumbnail of Compact Model Validation Strategies Based on Dedicated and Benchmark Circuit Blocks for the mm-Wave Frequency Range

2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015

This paper presents a methodology for compact model evaluation and validation at circuit level fo... more This paper presents a methodology for compact model evaluation and validation at circuit level for RF and mm-wave applications. Accurate compact models are a prerequisite for efficient circuit design but currently modeling engineers lack of suitable verification procedures. In this work we detail a methodology to fulfill these requirements together with circuit examples, starting from the simplest differential pair to the most advanced four stage differential LNA working at 220GHz. It is shown that a complete hierarchy of validation circuits (from the simplest circuit to the most complex) provides a new perspective with respect to the crucial task of model qualification but also directions for future compact model developments.

Research paper thumbnail of Design of On-Wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz

IEEE Transactions on Electron Devices, 2020

Research paper thumbnail of A Multiscale TCAD Approach for the Simulation of InP DHBTs and the Extraction of Their Transit Times

IEEE Transactions on Electron Devices, 2019

Research paper thumbnail of Comparison of On-Wafer TRL Calibration to ISS SOLT Calibration With Open-Short De-Embedding up to 500 GHz

IEEE Transactions on Terahertz Science and Technology, 2018

Sub-mm circuit design requires accurate on-wafer characterization of passive and active devices. ... more Sub-mm circuit design requires accurate on-wafer characterization of passive and active devices. In industry, characterization of these devices is often performed with offwafer SOLT calibration. In this work, validity of this characterization procedure above 110 GHz is investigated by an exhaustive study of on-wafer and alumina off-wafer calibration using measurement and electromagnetic (EM) simulation up to 500 GHz. The EM simulation is performed at two different levels, first at the intrinsic level of the devices under test for reference and afterward up to the probe level to simulate different standards used in the off-wafer calibration or in the on-wafer calibration in presence of the probe. Further, EM simulation data is calibrated with the same procedures and tools that is used in the measurement; therefore, it includes the probe-to-substrate coupling. In addition, precise EM model of a commercial impedance standard substrate (ISS) is developed and used to perform the SOLT calibration. A good agreement is observed between measurement and EM modelling for the off-wafer calibration as well as for the on-wafer calibration. Results clearly highlights a limitation of alumina off-wafer methodology above 200 GHz for characterization of Silicon based technologies. Finally a discussion is given on the pros and cons of the off-wafer and on-wafer methodologies.

Research paper thumbnail of Scalable Compact Modeling of III–V DHBTs: Prospective Figures of Merit Toward Terahertz Operation

IEEE Transactions on Electron Devices, 2018

We investigate the bias, temperature, and frequency dependence of two III-V double heterojunction... more We investigate the bias, temperature, and frequency dependence of two III-V double heterojunction bipolar transistors technologies based on InGaAs/InP and GaAsSb/InP processes, using a HiCuM/L2 compact model-based multigeometry scalable parameter extraction methodology. Very good agreement between the model simulations and experimental data is demonstrated. Transistor currents and junction capacitances show very good scaling, thereby allowing the separation of intrinsic and peripheral effects. Prediction of future III-V HBT technologies figuresof-merit is performed by using the generated scalable model card.

Research paper thumbnail of Meander type transmission line design for on-wafer TRL calibration

2016 46th European Microwave Conference (EuMC), 2016

An on-wafer TRL methodology based on meander type transmission lines was developed in the perspec... more An on-wafer TRL methodology based on meander type transmission lines was developed in the perspective of automated on-waver calibration. The TRL calibrations using meander lines and standard straight lines showed no significant difference when applied to characterize a single SiGe HBT up to 110 GHz under multiple bias points.

Research paper thumbnail of Sheet Resistance in BiCMOS Technology

Research paper thumbnail of Investigation of de-embedding procedure up to 110GHz

Face detection and tracking are of the most challenging problems of the object tracking field bec... more Face detection and tracking are of the most challenging problems of the object tracking field because of the large variability of faces and facial expressions. In this paper, two different algorithms for face tracking based on unscented Kalman filter (UKF) are proposed. The first proposed algorithm is UKF based on Viola-Jones algorithm. Viola-Jones is extremely fast feature computation, efficient feature selection, and scale and location invariant detector. The second proposed algorithm is UKF based on mean shift using the corrected background weighted histogram (CBWH) scheme. This scheme can effectively reduce background's interference in target localization and consequently can guarantee accurate localization of the target. The tracking step is completed using UKF that can estimate the next state with a high level of accuracy. So the two proposed algorithms are used to enhance the solution of face tracking problems. The performance of the two different proposed algorithms is evaluated with other well-known face tracking algorithms.

Research paper thumbnail of Investigation of De-embedding Methods up to 110GHz

As society has aged in Japan, residents of nursing homes are needing more advanced levels of care... more As society has aged in Japan, residents of nursing homes are needing more advanced levels of care, which is increasing costs. Accordingly, strategies to prevent further deterioration of health are necessary. The effects of indoor air temperature on health aspects such as blood pressure and mortality have recently attracted attention. We measured indoor air temperature and assessed changes in the level of care needed among 1337 residents in 27 nursing homes during winter 2015. The nursing homes were classified into two groups (warm or cold) according to UK National Health Service guidelines regarding indoor air temperature. Cox regression analysis revealed that residents in warm nursing homes were less likely to deteriorate to a higher level of care (HR = 0.48, 95% CI 0.31-0.75). The result suggests that policies to regulate indoor temperature may be one ingredient to delay declines in health of nursing home residents and reduce care costs.

Research paper thumbnail of A new transit time extraction algorithm based on matrix deembedding techniques

Research paper thumbnail of Final Version MWEISS Submission Number 130

Research paper thumbnail of EuMIC 02-2 ARDOUIN Pres

Research paper thumbnail of Modeling and parameter extraction of SiGe: C HBT’s with HICUM for the emerging terahertz era

ABSTRACT This paper presents a status of the HICUM model development activities (within the DOTFI... more ABSTRACT This paper presents a status of the HICUM model development activities (within the DOTFIVE project) for future technologies. Physics based scalable model libraries are realized for two of the most advanced SiGe:C HBT processes currently available. The parameter extraction methodology is described via two meaningful examples. Measurement and simulation comparisons are shown.

Research paper thumbnail of Characterization of intra device mutual thermal coupling in multi finger SiGe:C HBTs

2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013

This paper studies the mutual coupling in trench isolated multi-emitter bipolar transistors fabri... more This paper studies the mutual coupling in trench isolated multi-emitter bipolar transistors fabricated in a Si/SiGe:C HBT technology STMicroelectronics featuring f T and f max of ~300GHz and ~400GHz, respectively. Thermal coupling parameters are extracted using three-dimensional (3D) thermal TCAD simulations. The obtained parameters are implemented in a distributed transistor model that considers self-heating as well as thermal coupling between emitter fingers. Very good agreement is achieved between circuit simulations and DC measurements carried out on an in-house designed test structure.

Research paper thumbnail of High accuracy temperature bipolar modeling for demanding Bandgap application

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007

VDD reduction in advanced CMOS IC's push for reduced temperature stabilit... more VDD reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for IC temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.

Research paper thumbnail of From measurement to intrinsic device characteristics: Test structures and parasitic determination

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008

mm-Wave applications claim for accurate and reliable device models for their very high frequency ... more mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described

Research paper thumbnail of New test structures for extraction of base sheet resistance in BiCMOS technology

2006 IEEE International Conference on Microelectronic Test Structures, 2006

ABSTRACT For process monitoring and device modeling, a new method to determine the different comp... more ABSTRACT For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements. This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.

Research paper thumbnail of 250-GHz self-aligned Si/SiGeC HBT featuring an all-implanted collector

2006 Bipolar/BiCMOS Circuits and Technology Meeting, 2006

Abstract This paper presents investigations led to simplify the collector module of SiGeC HBTs in... more Abstract This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record f T and f max (> 250 GHz)

Research paper thumbnail of Investigation of high frequency coupling between probe tips and wafer surface

2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009

This paper presents an investigation of the coupling between probe tips and wafer surface through... more This paper presents an investigation of the coupling between probe tips and wafer surface through EM-simulation and compares the simulation results to measurements. It is pointed out that the results are very dependent on the adjacent structures lying under the probe tips. Different solutions are analyzed to master and/or reduce the coupling and ensure reproducibility.

Research paper thumbnail of New Method for Oxide Capacitance Extraction

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007

Based on different geometries of bipolar transistors, a new scalable method to determine the para... more Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results

Research paper thumbnail of Compact Model Validation Strategies Based on Dedicated and Benchmark Circuit Blocks for the mm-Wave Frequency Range

2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015

This paper presents a methodology for compact model evaluation and validation at circuit level fo... more This paper presents a methodology for compact model evaluation and validation at circuit level for RF and mm-wave applications. Accurate compact models are a prerequisite for efficient circuit design but currently modeling engineers lack of suitable verification procedures. In this work we detail a methodology to fulfill these requirements together with circuit examples, starting from the simplest differential pair to the most advanced four stage differential LNA working at 220GHz. It is shown that a complete hierarchy of validation circuits (from the simplest circuit to the most complex) provides a new perspective with respect to the crucial task of model qualification but also directions for future compact model developments.

Research paper thumbnail of Design of On-Wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz

IEEE Transactions on Electron Devices, 2020

Research paper thumbnail of A Multiscale TCAD Approach for the Simulation of InP DHBTs and the Extraction of Their Transit Times

IEEE Transactions on Electron Devices, 2019

Research paper thumbnail of Comparison of On-Wafer TRL Calibration to ISS SOLT Calibration With Open-Short De-Embedding up to 500 GHz

IEEE Transactions on Terahertz Science and Technology, 2018

Sub-mm circuit design requires accurate on-wafer characterization of passive and active devices. ... more Sub-mm circuit design requires accurate on-wafer characterization of passive and active devices. In industry, characterization of these devices is often performed with offwafer SOLT calibration. In this work, validity of this characterization procedure above 110 GHz is investigated by an exhaustive study of on-wafer and alumina off-wafer calibration using measurement and electromagnetic (EM) simulation up to 500 GHz. The EM simulation is performed at two different levels, first at the intrinsic level of the devices under test for reference and afterward up to the probe level to simulate different standards used in the off-wafer calibration or in the on-wafer calibration in presence of the probe. Further, EM simulation data is calibrated with the same procedures and tools that is used in the measurement; therefore, it includes the probe-to-substrate coupling. In addition, precise EM model of a commercial impedance standard substrate (ISS) is developed and used to perform the SOLT calibration. A good agreement is observed between measurement and EM modelling for the off-wafer calibration as well as for the on-wafer calibration. Results clearly highlights a limitation of alumina off-wafer methodology above 200 GHz for characterization of Silicon based technologies. Finally a discussion is given on the pros and cons of the off-wafer and on-wafer methodologies.

Research paper thumbnail of Scalable Compact Modeling of III–V DHBTs: Prospective Figures of Merit Toward Terahertz Operation

IEEE Transactions on Electron Devices, 2018

We investigate the bias, temperature, and frequency dependence of two III-V double heterojunction... more We investigate the bias, temperature, and frequency dependence of two III-V double heterojunction bipolar transistors technologies based on InGaAs/InP and GaAsSb/InP processes, using a HiCuM/L2 compact model-based multigeometry scalable parameter extraction methodology. Very good agreement between the model simulations and experimental data is demonstrated. Transistor currents and junction capacitances show very good scaling, thereby allowing the separation of intrinsic and peripheral effects. Prediction of future III-V HBT technologies figuresof-merit is performed by using the generated scalable model card.

Research paper thumbnail of Meander type transmission line design for on-wafer TRL calibration

2016 46th European Microwave Conference (EuMC), 2016

An on-wafer TRL methodology based on meander type transmission lines was developed in the perspec... more An on-wafer TRL methodology based on meander type transmission lines was developed in the perspective of automated on-waver calibration. The TRL calibrations using meander lines and standard straight lines showed no significant difference when applied to characterize a single SiGe HBT up to 110 GHz under multiple bias points.

Research paper thumbnail of Sheet Resistance in BiCMOS Technology

Research paper thumbnail of Investigation of de-embedding procedure up to 110GHz

Face detection and tracking are of the most challenging problems of the object tracking field bec... more Face detection and tracking are of the most challenging problems of the object tracking field because of the large variability of faces and facial expressions. In this paper, two different algorithms for face tracking based on unscented Kalman filter (UKF) are proposed. The first proposed algorithm is UKF based on Viola-Jones algorithm. Viola-Jones is extremely fast feature computation, efficient feature selection, and scale and location invariant detector. The second proposed algorithm is UKF based on mean shift using the corrected background weighted histogram (CBWH) scheme. This scheme can effectively reduce background's interference in target localization and consequently can guarantee accurate localization of the target. The tracking step is completed using UKF that can estimate the next state with a high level of accuracy. So the two proposed algorithms are used to enhance the solution of face tracking problems. The performance of the two different proposed algorithms is evaluated with other well-known face tracking algorithms.

Research paper thumbnail of Investigation of De-embedding Methods up to 110GHz

As society has aged in Japan, residents of nursing homes are needing more advanced levels of care... more As society has aged in Japan, residents of nursing homes are needing more advanced levels of care, which is increasing costs. Accordingly, strategies to prevent further deterioration of health are necessary. The effects of indoor air temperature on health aspects such as blood pressure and mortality have recently attracted attention. We measured indoor air temperature and assessed changes in the level of care needed among 1337 residents in 27 nursing homes during winter 2015. The nursing homes were classified into two groups (warm or cold) according to UK National Health Service guidelines regarding indoor air temperature. Cox regression analysis revealed that residents in warm nursing homes were less likely to deteriorate to a higher level of care (HR = 0.48, 95% CI 0.31-0.75). The result suggests that policies to regulate indoor temperature may be one ingredient to delay declines in health of nursing home residents and reduce care costs.

Research paper thumbnail of A new transit time extraction algorithm based on matrix deembedding techniques

Research paper thumbnail of Final Version MWEISS Submission Number 130

Research paper thumbnail of EuMIC 02-2 ARDOUIN Pres

Research paper thumbnail of Modeling and parameter extraction of SiGe: C HBT’s with HICUM for the emerging terahertz era

ABSTRACT This paper presents a status of the HICUM model development activities (within the DOTFI... more ABSTRACT This paper presents a status of the HICUM model development activities (within the DOTFIVE project) for future technologies. Physics based scalable model libraries are realized for two of the most advanced SiGe:C HBT processes currently available. The parameter extraction methodology is described via two meaningful examples. Measurement and simulation comparisons are shown.

Research paper thumbnail of Characterization of intra device mutual thermal coupling in multi finger SiGe:C HBTs

2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013

This paper studies the mutual coupling in trench isolated multi-emitter bipolar transistors fabri... more This paper studies the mutual coupling in trench isolated multi-emitter bipolar transistors fabricated in a Si/SiGe:C HBT technology STMicroelectronics featuring f T and f max of ~300GHz and ~400GHz, respectively. Thermal coupling parameters are extracted using three-dimensional (3D) thermal TCAD simulations. The obtained parameters are implemented in a distributed transistor model that considers self-heating as well as thermal coupling between emitter fingers. Very good agreement is achieved between circuit simulations and DC measurements carried out on an in-house designed test structure.

Research paper thumbnail of High accuracy temperature bipolar modeling for demanding Bandgap application

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007

VDD reduction in advanced CMOS IC's push for reduced temperature stabilit... more VDD reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for IC temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.

Research paper thumbnail of From measurement to intrinsic device characteristics: Test structures and parasitic determination

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008

mm-Wave applications claim for accurate and reliable device models for their very high frequency ... more mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described

Research paper thumbnail of New test structures for extraction of base sheet resistance in BiCMOS technology

2006 IEEE International Conference on Microelectronic Test Structures, 2006

ABSTRACT For process monitoring and device modeling, a new method to determine the different comp... more ABSTRACT For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements. This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.

Research paper thumbnail of 250-GHz self-aligned Si/SiGeC HBT featuring an all-implanted collector

2006 Bipolar/BiCMOS Circuits and Technology Meeting, 2006

Abstract This paper presents investigations led to simplify the collector module of SiGeC HBTs in... more Abstract This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record f T and f max (> 250 GHz)

Research paper thumbnail of Investigation of high frequency coupling between probe tips and wafer surface

2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009

This paper presents an investigation of the coupling between probe tips and wafer surface through... more This paper presents an investigation of the coupling between probe tips and wafer surface through EM-simulation and compares the simulation results to measurements. It is pointed out that the results are very dependent on the adjacent structures lying under the probe tips. Different solutions are analyzed to master and/or reduce the coupling and ensure reproducibility.

Research paper thumbnail of New Method for Oxide Capacitance Extraction

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007

Based on different geometries of bipolar transistors, a new scalable method to determine the para... more Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results