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Papers by Claude Thibeault

Research paper thumbnail of An efficient FPGA implementation of a pulse-shaping IIR filter

Research paper thumbnail of Towards an efficient SEU effects emulation on SRAM-based FPGAs

Microelectronics Reliability, Nov 1, 2016

A novel fault injection approach, reproducing results obtained from radiation ground testing whil... more A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to '0' and those set to '1'. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to '1' are approximately twice as sensitive as bits set to '0'. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.

Research paper thumbnail of An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs

A new fault injection approach targeting the LUTs configuration bits of the Xilinx SRAM-based FPG... more A new fault injection approach targeting the LUTs configuration bits of the Xilinx SRAM-based FPGAs is presented. It allows identifying all the configuration bits used by the LUTs of a specific design to inject Single Event Upsets (SEUs) and Multiple Bit Upsets (MBUs). The identification of the LUTs configuration bits is done by comparing the EBC files of a specific design before and after modifying its XDL file by inverting the LUTs logic functions. The fault injection is ensured by a fault injection macro provided by Xilinx. A Python script is deployed to automate the fault injection procedure. The proposed approach does not require extra tools to identify LUTs configuration bits and offers a 100% of fault coverage and is applicable to new Xilinx FPGA generations.

Research paper thumbnail of Multi-equalization a powerful adaptive filtering for time varying wireless channels

Research paper thumbnail of Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis

This paper presents a new and highly efficient approach for the estimation by fault injection of ... more This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

Research paper thumbnail of On new current signatures and adaptive test technique combination

This paper proposes new current signatures for test purposes. It estimates their capabilities in ... more This paper proposes new current signatures for test purposes. It estimates their capabilities in the detection of additional current caused by weak resistive active and passive defects, when used separately and in combination with other current-based test techniques. Estimation results based in part on actual IDDQ measurements show that current-based test technique combinations allow reliable detection of smaller current deltas

Research paper thumbnail of Can the current behavior of faulty and fault-free ICs and the impact on diagnosis

The purpose of this paper is to analyze the current behavior of faulty and fault free integrated ... more The purpose of this paper is to analyze the current behavior of faulty and fault free integrated circuits (ICs) and its impact on diagnosis. More specifically, we first show that normal sub-threshold current can be modeled by a Gaussian distribution. Then, we investigate faulty IC current variations caused to the load connected to nodes involved in bridging faults. Finally, we

Research paper thumbnail of Autogenerating software polar decoders

Polar decoders are well suited for high-speed software implementations. In this work, we present ... more Polar decoders are well suited for high-speed software implementations. In this work, we present a framework for generating fully-unrolled software polar decoders with branchless data flow. We discuss the memory layout of data in these decoders and show the optimization techniques used. At 335 Mbps, when decoding a (2048, 1707) polar code, the resulting decoder has more than twice the speed of the state of the art floating-point software polar decoder. Index Terms-polar codes, decoder, software α l [i] = f (α v [i], α v [i + N v/2]) = sign(α v [i])sign(α v [i + N v/2]) min(|α v [i]|, |α v [i + N v/2]|); where N v is the size of the corresponding constituent code and α v the LLR input to the current node. Messages to a right

Research paper thumbnail of A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs

Polar codes are capacity-achieving error-correcting codes with an explicit construction that can ... more Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. Dedicated hardware is added to efficiently decode new constituent codes. Also, we use polar code construction alteration to further improve the latency and throughput. A polar decoder for a (1024, 512) code is implemented on two different FPGAs. It has 25% lower latency over the previous work and a coded throughput of 436 Mbps and 638 Mbps on the Xilinx Virtex 6 and Altera Stratix IV FPGAs, respectively.

Research paper thumbnail of Fast software polar decoders

Research paper thumbnail of Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays

IEEE Transactions on Aerospace and Electronic Systems, Apr 1, 2016

Due to continued miniaturization, semiconductor-based components used in high-performance digital... more Due to continued miniaturization, semiconductor-based components used in high-performance digital microelectronics are becoming increasingly sensitive to cosmic rays and solar particle events. In the context of high-altitude flight control systems based on fly-by-wire techniques, this may produce sensor noise or affect actuator control signals. Although the consequences so far have been simply reductions in aircraft performance, catastrophic scenarios may be envisioned. In this article, we propose a novel architecture for a fault-tolerant flight control system able to detect and compensate for cosmic ray-induced multiple-bit upsets that affect actuator control signals in modern fly-by-wire avionics systems while assuming that the actuator itself remains healthy. A fault detection and diagnosis procedure was designed using a geometric approach combined with an extended multiple-model adaptive estimation technique. This procedure is able to process multiple faulty actuator-control signals and identify their parameters. The parameters thus obtained are then used with a reconfigurable sliding-mode control to compensate for such errors by mobilizing the remaining actuators' healthy control signals. Lyapunov stability theory is used to analyze the closed-loop system stability. Simulation results using Matlab /Simulink showed the effectiveness of the proposed approach in the case of a system challenged with double faults.

Research paper thumbnail of Diagnosis method based on ΔIddq probabilistic signatures: experimental results

... 1131 SM Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-... more ... 1131 SM Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, New York ... [16] D. Josephson, M. Storey, and D. Dixon, “Microprocessor IDDQ Testing ... [20] C. Thibeault, “A Novel Probabilistic Approach for IC Diagnosis Based on Differential ...

Research paper thumbnail of A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures

In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quie... more In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quiescent current (IDDQ) signatures. Unlike the previous diagnosis approaches using current, this approach, using the maximum likelihood estimation, provides a solid framework allowing to quantify its robustness with respect to current measurement variations. The differential nature of the signatures allows to treat subthreshold leakage currents as

Research paper thumbnail of Detection and location of embedded critical paths by signal processing of IDD

Research paper thumbnail of Un nouvel algorithme de décodage pour les codes convolutionnels

Research paper thumbnail of Towards a realistic SEU effects emulation on SRAM Based FPGAs

HAL (Le Centre pour la Communication Scientifique Directe), Jul 14, 2014

International audienc

Research paper thumbnail of Modeling and Dynamic Scheduling of Turbo Decoding for a Homogeneous Multiprocessor Platform

Research paper thumbnail of A successful industry-university collaboration

Research paper thumbnail of Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG

arXiv (Cornell University), Oct 1, 2013

Research paper thumbnail of Design of a Multi-User Multi-Carrier Differential Chaos Shift Keying Communication System

arXiv (Cornell University), Mar 7, 2013

In this paper, a multi user Multi-Carrier Differential Chaos Shift Keying (MC-DCSK) modulation is... more In this paper, a multi user Multi-Carrier Differential Chaos Shift Keying (MC-DCSK) modulation is presented. The system endeavors to provide a good trade-off between robustness, energy efficiency and high data rate, while still being simple. In this architecture of MC-DCSK system, for each user, chaotic reference sequence is transmitted over a predefined subcarrier frequency. Multiple modulated data streams are transmitted over the remaining subcarriers allocated for each user. This transmitter structure saves energy and increases the spectral efficiency of the conventional DCSK system.

Research paper thumbnail of An efficient FPGA implementation of a pulse-shaping IIR filter

Research paper thumbnail of Towards an efficient SEU effects emulation on SRAM-based FPGAs

Microelectronics Reliability, Nov 1, 2016

A novel fault injection approach, reproducing results obtained from radiation ground testing whil... more A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to '0' and those set to '1'. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to '1' are approximately twice as sensitive as bits set to '0'. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.

Research paper thumbnail of An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs

A new fault injection approach targeting the LUTs configuration bits of the Xilinx SRAM-based FPG... more A new fault injection approach targeting the LUTs configuration bits of the Xilinx SRAM-based FPGAs is presented. It allows identifying all the configuration bits used by the LUTs of a specific design to inject Single Event Upsets (SEUs) and Multiple Bit Upsets (MBUs). The identification of the LUTs configuration bits is done by comparing the EBC files of a specific design before and after modifying its XDL file by inverting the LUTs logic functions. The fault injection is ensured by a fault injection macro provided by Xilinx. A Python script is deployed to automate the fault injection procedure. The proposed approach does not require extra tools to identify LUTs configuration bits and offers a 100% of fault coverage and is applicable to new Xilinx FPGA generations.

Research paper thumbnail of Multi-equalization a powerful adaptive filtering for time varying wireless channels

Research paper thumbnail of Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis

This paper presents a new and highly efficient approach for the estimation by fault injection of ... more This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

Research paper thumbnail of On new current signatures and adaptive test technique combination

This paper proposes new current signatures for test purposes. It estimates their capabilities in ... more This paper proposes new current signatures for test purposes. It estimates their capabilities in the detection of additional current caused by weak resistive active and passive defects, when used separately and in combination with other current-based test techniques. Estimation results based in part on actual IDDQ measurements show that current-based test technique combinations allow reliable detection of smaller current deltas

Research paper thumbnail of Can the current behavior of faulty and fault-free ICs and the impact on diagnosis

The purpose of this paper is to analyze the current behavior of faulty and fault free integrated ... more The purpose of this paper is to analyze the current behavior of faulty and fault free integrated circuits (ICs) and its impact on diagnosis. More specifically, we first show that normal sub-threshold current can be modeled by a Gaussian distribution. Then, we investigate faulty IC current variations caused to the load connected to nodes involved in bridging faults. Finally, we

Research paper thumbnail of Autogenerating software polar decoders

Polar decoders are well suited for high-speed software implementations. In this work, we present ... more Polar decoders are well suited for high-speed software implementations. In this work, we present a framework for generating fully-unrolled software polar decoders with branchless data flow. We discuss the memory layout of data in these decoders and show the optimization techniques used. At 335 Mbps, when decoding a (2048, 1707) polar code, the resulting decoder has more than twice the speed of the state of the art floating-point software polar decoder. Index Terms-polar codes, decoder, software α l [i] = f (α v [i], α v [i + N v/2]) = sign(α v [i])sign(α v [i + N v/2]) min(|α v [i]|, |α v [i + N v/2]|); where N v is the size of the corresponding constituent code and α v the LLR input to the current node. Messages to a right

Research paper thumbnail of A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs

Polar codes are capacity-achieving error-correcting codes with an explicit construction that can ... more Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. Dedicated hardware is added to efficiently decode new constituent codes. Also, we use polar code construction alteration to further improve the latency and throughput. A polar decoder for a (1024, 512) code is implemented on two different FPGAs. It has 25% lower latency over the previous work and a coded throughput of 436 Mbps and 638 Mbps on the Xilinx Virtex 6 and Altera Stratix IV FPGAs, respectively.

Research paper thumbnail of Fast software polar decoders

Research paper thumbnail of Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays

IEEE Transactions on Aerospace and Electronic Systems, Apr 1, 2016

Due to continued miniaturization, semiconductor-based components used in high-performance digital... more Due to continued miniaturization, semiconductor-based components used in high-performance digital microelectronics are becoming increasingly sensitive to cosmic rays and solar particle events. In the context of high-altitude flight control systems based on fly-by-wire techniques, this may produce sensor noise or affect actuator control signals. Although the consequences so far have been simply reductions in aircraft performance, catastrophic scenarios may be envisioned. In this article, we propose a novel architecture for a fault-tolerant flight control system able to detect and compensate for cosmic ray-induced multiple-bit upsets that affect actuator control signals in modern fly-by-wire avionics systems while assuming that the actuator itself remains healthy. A fault detection and diagnosis procedure was designed using a geometric approach combined with an extended multiple-model adaptive estimation technique. This procedure is able to process multiple faulty actuator-control signals and identify their parameters. The parameters thus obtained are then used with a reconfigurable sliding-mode control to compensate for such errors by mobilizing the remaining actuators' healthy control signals. Lyapunov stability theory is used to analyze the closed-loop system stability. Simulation results using Matlab /Simulink showed the effectiveness of the proposed approach in the case of a system challenged with double faults.

Research paper thumbnail of Diagnosis method based on ΔIddq probabilistic signatures: experimental results

... 1131 SM Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-... more ... 1131 SM Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, New York ... [16] D. Josephson, M. Storey, and D. Dixon, “Microprocessor IDDQ Testing ... [20] C. Thibeault, “A Novel Probabilistic Approach for IC Diagnosis Based on Differential ...

Research paper thumbnail of A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures

In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quie... more In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quiescent current (IDDQ) signatures. Unlike the previous diagnosis approaches using current, this approach, using the maximum likelihood estimation, provides a solid framework allowing to quantify its robustness with respect to current measurement variations. The differential nature of the signatures allows to treat subthreshold leakage currents as

Research paper thumbnail of Detection and location of embedded critical paths by signal processing of IDD

Research paper thumbnail of Un nouvel algorithme de décodage pour les codes convolutionnels

Research paper thumbnail of Towards a realistic SEU effects emulation on SRAM Based FPGAs

HAL (Le Centre pour la Communication Scientifique Directe), Jul 14, 2014

International audienc

Research paper thumbnail of Modeling and Dynamic Scheduling of Turbo Decoding for a Homogeneous Multiprocessor Platform

Research paper thumbnail of A successful industry-university collaboration

Research paper thumbnail of Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG

arXiv (Cornell University), Oct 1, 2013

Research paper thumbnail of Design of a Multi-User Multi-Carrier Differential Chaos Shift Keying Communication System

arXiv (Cornell University), Mar 7, 2013

In this paper, a multi user Multi-Carrier Differential Chaos Shift Keying (MC-DCSK) modulation is... more In this paper, a multi user Multi-Carrier Differential Chaos Shift Keying (MC-DCSK) modulation is presented. The system endeavors to provide a good trade-off between robustness, energy efficiency and high data rate, while still being simple. In this architecture of MC-DCSK system, for each user, chaotic reference sequence is transmitted over a predefined subcarrier frequency. Multiple modulated data streams are transmitted over the remaining subcarriers allocated for each user. This transmitter structure saves energy and increases the spectral efficiency of the conventional DCSK system.