N. Collaert - Academia.edu (original) (raw)
Papers by N. Collaert
ECS Transactions, 2014
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ECS Transactions, 2007
ABSTRACT
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2008 IEEE International SOI Conference, 2008
In this paper we present the first complex mixed-signal FinFET circuit (&... more In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching
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Microelectronic Engineering, 2015
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Journal of Crystal Growth, 2015
ABSTRACT
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ECS Transactions, 2015
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2015 IEEE International Reliability Physics Symposium, 2015
ABSTRACT
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ECS Transactions, 2007
Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective. [ECS Tr... more Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective. [ECS Transactions 9, 19 (2007)]. Marcelo A. Pavanello, Joao A. Martino, E. Simoen, R. Rooyackers, N. Collaert, C. Claeys. Abstract. ...
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2005 IEEE International SOI Conference Proceedings, 2005
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2009 IEEE International SOI Conference, 2009
This paper studies the influence of the 45deg substrate rotation on the analog parameters of n-ty... more This paper studies the influence of the 45deg substrate rotation on the analog parameters of n-type and p-type triple-gate FinFETs with HfSiON gate dielectric, TiN gate material and undoped body. Tall triple-gate n-type and p-type FinFETs were fabricated on SOI wafers with 150 nm thick buried oxide. The fin height (HFin) is 65 nm for all devices. It has been
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2009 IEEE International SOI Conference, 2009
ABSTRACT
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Applied Physics Letters, 2014
ABSTRACT We show that bulk semiconductor materials do not allow perfectly complementary p- and n-... more ABSTRACT We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.
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Applied Physics Letters, 2014
ABSTRACT High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned... more ABSTRACT High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned structures. The patterned wafers have a V-shape Si (111) surface obtained by Tetramethylammonium hydroxide etching. By employing a SiCoNi™ pre-epi clean and two-step growth procedure (low temperature buffer and high temperature main layer), defects are effectively confined at the trench bottom, leaving a dislocation-free GaAs layer at the upper part. The high crystal quality is confirmed by transmission electron microscopy. Scanning spreading resistance microscopy indicates a high resistance of GaAs. The process conditions and GaAs material quality are highly compatible with Si technology platform.
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A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction condu... more A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is degraded at small gate length in sub 100nm FinFETs, as was already found for GAA, FD-SOI and DG-MOS devices. By proper extraction technique, sidewall and top conductions are analyzed, showing that sidewall mobility is
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2011 21st International Conference on Noise and Fluctuations, 2011
This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- a... more This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- and p-channel triple-gate FinFET transistors with 25 nm fin-width, 65 nm fin-height, a high-k dielectric / metal gate stack, strained and unstrained substrates. These investigations allow evaluating the quality of the gate oxide interface, to identify defects in the silicon film
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2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014
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Solid-State Electronics, 2011
This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and Ti... more This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a
Bookmarks Related papers MentionsView impact
ECS Transactions, 2014
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ECS Transactions, 2007
ABSTRACT
Bookmarks Related papers MentionsView impact
2008 IEEE International SOI Conference, 2008
In this paper we present the first complex mixed-signal FinFET circuit (&... more In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching
Bookmarks Related papers MentionsView impact
Microelectronic Engineering, 2015
Bookmarks Related papers MentionsView impact
Journal of Crystal Growth, 2015
ABSTRACT
Bookmarks Related papers MentionsView impact
ECS Transactions, 2015
Bookmarks Related papers MentionsView impact
2015 IEEE International Reliability Physics Symposium, 2015
ABSTRACT
Bookmarks Related papers MentionsView impact
ECS Transactions, 2007
Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective. [ECS Tr... more Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective. [ECS Transactions 9, 19 (2007)]. Marcelo A. Pavanello, Joao A. Martino, E. Simoen, R. Rooyackers, N. Collaert, C. Claeys. Abstract. ...
Bookmarks Related papers MentionsView impact
2005 IEEE International SOI Conference Proceedings, 2005
Bookmarks Related papers MentionsView impact
2009 IEEE International SOI Conference, 2009
This paper studies the influence of the 45deg substrate rotation on the analog parameters of n-ty... more This paper studies the influence of the 45deg substrate rotation on the analog parameters of n-type and p-type triple-gate FinFETs with HfSiON gate dielectric, TiN gate material and undoped body. Tall triple-gate n-type and p-type FinFETs were fabricated on SOI wafers with 150 nm thick buried oxide. The fin height (HFin) is 65 nm for all devices. It has been
Bookmarks Related papers MentionsView impact
2009 IEEE International SOI Conference, 2009
ABSTRACT
Bookmarks Related papers MentionsView impact
Applied Physics Letters, 2014
ABSTRACT We show that bulk semiconductor materials do not allow perfectly complementary p- and n-... more ABSTRACT We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration.
Bookmarks Related papers MentionsView impact
Applied Physics Letters, 2014
ABSTRACT High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned... more ABSTRACT High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned structures. The patterned wafers have a V-shape Si (111) surface obtained by Tetramethylammonium hydroxide etching. By employing a SiCoNi™ pre-epi clean and two-step growth procedure (low temperature buffer and high temperature main layer), defects are effectively confined at the trench bottom, leaving a dislocation-free GaAs layer at the upper part. The high crystal quality is confirmed by transmission electron microscopy. Scanning spreading resistance microscopy indicates a high resistance of GaAs. The process conditions and GaAs material quality are highly compatible with Si technology platform.
Bookmarks Related papers MentionsView impact
A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction condu... more A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is degraded at small gate length in sub 100nm FinFETs, as was already found for GAA, FD-SOI and DG-MOS devices. By proper extraction technique, sidewall and top conductions are analyzed, showing that sidewall mobility is
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
2011 21st International Conference on Noise and Fluctuations, 2011
This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- a... more This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- and p-channel triple-gate FinFET transistors with 25 nm fin-width, 65 nm fin-height, a high-k dielectric / metal gate stack, strained and unstrained substrates. These investigations allow evaluating the quality of the gate oxide interface, to identify defects in the silicon film
Bookmarks Related papers MentionsView impact
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014
Bookmarks Related papers MentionsView impact
Solid-State Electronics, 2011
This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and Ti... more This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a
Bookmarks Related papers MentionsView impact