Costas Argyrides - Academia.edu (original) (raw)

Papers by Costas Argyrides

Research paper thumbnail of Matrix codes: Multiple bit upsets tolerant method for sram memories

This paper presents a high level method called Matrix code to protect SRAM-based memories against... more This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and ...

Research paper thumbnail of Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs

… , 2007. IPDPS 2007. …, Jan 1, 2007

Research paper thumbnail of Multiple upsets tolerance in SRAM memory

Circuits and Systems, …, Jan 1, 2007

I. I NTRO DU C TIO N As process technology scales to small nanometers, high-density, low cost, hi... more I. I NTRO DU C TIO N As process technology scales to small nanometers, high-density, low cost, high performance integrated circuits, characterized by high operating frequencies, low voltage levels and small noise margins will be increasingly susceptible to temporary faults [9]. In ...

Research paper thumbnail of Embedding current monitoring in h-tree RAM architecture for multiple seu tolerance and reliability improvement

On-Line Testing …, Jan 1, 2008

Abstract In this paper, we present a new technique to improve the reliability of H-tree SRAM memo... more Abstract In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory ...

Research paper thumbnail of Single element correction in sorting algorithms with minimum delay overhead

Test Workshop, 2009. …, Jan 1, 2009

Page 1. Single Element Correction in Sorting Algorithms with Minimum Delay Overhead Costas A. Arg... more Page 1. Single Element Correction in Sorting Algorithms with Minimum Delay Overhead Costas A. Argyrides1, Carlos A. Lisboa2, Dhiraj K. Pradhan1, Luigi Carro2 1Department of Computer Science of the University of Bristol ...

Research paper thumbnail of A soft error robust and power aware memory design

Proceedings of the 20th …, Jan 1, 2007

Research paper thumbnail of Increasing memory yield in future technologies through innovative design

Quality of Electronic …, Jan 1, 2009

Abstract Future technologies, with ever shrinking devices and higher densities, bring along highe... more Abstract Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and ...

Research paper thumbnail of Highly Reliable Power Aware Memory Design

On-Line Testing Symposium, 2007 …, Jan 1, 2007

I. I NTRODUCTION The design of low-power RAM is crucial for the semiconductor industry. Over 50 p... more I. I NTRODUCTION The design of low-power RAM is crucial for the semiconductor industry. Over 50 percent of a modern System-on-a Chip (SOC) is currently occupied by memory and the ratio is increasing. In current microprocessors, more than 30 percent of the chip area is ...

Research paper thumbnail of Improved decoding algorithm for high reliable reed muller coding

SOC Conference, 2007 IEEE …, Jan 1, 2008

Abstract A new decoding technique for triple error Reed-Muller codes is proposed. In the best of ... more Abstract A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip triple error correcting scheme is reported. We've compared the area, delay and power overhead for ...

Research paper thumbnail of Area Reliability Trade-Off in Improved Reed Muller Coding

Embedded Computer Systems: …, Jan 1, 2008

M. Berekovic, N. Dimopoulos, and S. Wong (Eds.): SAMOS 2008, LNCS 5114, pp. 116–125, 2008. © Spri... more M. Berekovic, N. Dimopoulos, and S. Wong (Eds.): SAMOS 2008, LNCS 5114, pp. 116–125, 2008. © Springer-Verlag Berlin Heidelberg 2008 ... Area Reliability Trade-Off in Improved Reed ... Costas Argyrides2, Stephania Loizidou1, and Dhiraj K. Pradhan2

Research paper thumbnail of Improved Yield in Nanotechnology Circuits Using Non-square Meshes

Proceedings of the 2010 …, Jan 1, 2010

Abstract—Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowire... more Abstract—Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected ...

Research paper thumbnail of CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

Circuits and Systems …, Jan 1, 2007

Abstract— This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high en... more Abstract— This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the ...

Research paper thumbnail of Application Specific-Area Reliability Trade-Off in Improved Reed Muller Coding

Lecture Notes in …, Jan 1, 2008

Research paper thumbnail of 26th IEEE VLSI Test Symposium (vts 2008)

For technologies beyond the 45 nm node, radiation induced transients will last longer than one cl... more For technologies beyond the 45 nm node, radiation induced transients will last longer than one clock cycle. In this scenario, temporal redundancy techniques will no longer be able to cope with radiation induced soft errors, while spatial redundancy techniques still impose high ...

Research paper thumbnail of 2008 Reviewers List

IEEE TRANSACTIONS …, Jan 1, 2009

... Daniel Brown Sharon Browning Soren Brunak Vladimir Brusic Kenneth Bryan David Bryant Jeremy B... more ... Daniel Brown Sharon Browning Soren Brunak Vladimir Brusic Kenneth Bryan David Bryant Jeremy Buhler Ralf Bundschuh Chris Bystroff ... Tony Chiang Benny Chor Ferdinando Cicalese Matteo Comin Lenore Cowen Maxime Crochemore Lisa Croner Miklos Csuros Xinping Cui ...

Research paper thumbnail of Multiple Event Upsets Aware FPGAs Using Protected Schemes

Research paper thumbnail of 2009 10th International Symposium on Quality of Electronic Design

Abstract Future technologies, with ever shrinking devices and higher densities, bring along highe... more Abstract Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and ...

Research paper thumbnail of 2010 IEEE Annual Symposium on VLSI

Abstract— Reconfigurable analog-to-digital converters (ADC) have been receiving increased attenti... more Abstract— Reconfigurable analog-to-digital converters (ADC) have been receiving increased attention in the research community for the capability to adapt to continuously varying signal processing requirements. The reconfigurable ADC is particularly advantageous in ...

Research paper thumbnail of Matrix-Based Codes for Adjacent Error Correction

Nuclear Science, …, Jan 1, 2010

Page 1. 2106 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010 Matrix-Based Codes... more Page 1. 2106 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010 Matrix-Based Codes for Adjacent Error Correction Costas A. Argyrides, Pedro Reviriego, Dhiraj K. Pradhan, and Juan Antonio Maestro ...

Research paper thumbnail of Reviewers List

Computers, IEEE …, Jan 1, 2007

Research paper thumbnail of Matrix codes: Multiple bit upsets tolerant method for sram memories

This paper presents a high level method called Matrix code to protect SRAM-based memories against... more This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and ...

Research paper thumbnail of Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs

… , 2007. IPDPS 2007. …, Jan 1, 2007

Research paper thumbnail of Multiple upsets tolerance in SRAM memory

Circuits and Systems, …, Jan 1, 2007

I. I NTRO DU C TIO N As process technology scales to small nanometers, high-density, low cost, hi... more I. I NTRO DU C TIO N As process technology scales to small nanometers, high-density, low cost, high performance integrated circuits, characterized by high operating frequencies, low voltage levels and small noise margins will be increasingly susceptible to temporary faults [9]. In ...

Research paper thumbnail of Embedding current monitoring in h-tree RAM architecture for multiple seu tolerance and reliability improvement

On-Line Testing …, Jan 1, 2008

Abstract In this paper, we present a new technique to improve the reliability of H-tree SRAM memo... more Abstract In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory ...

Research paper thumbnail of Single element correction in sorting algorithms with minimum delay overhead

Test Workshop, 2009. …, Jan 1, 2009

Page 1. Single Element Correction in Sorting Algorithms with Minimum Delay Overhead Costas A. Arg... more Page 1. Single Element Correction in Sorting Algorithms with Minimum Delay Overhead Costas A. Argyrides1, Carlos A. Lisboa2, Dhiraj K. Pradhan1, Luigi Carro2 1Department of Computer Science of the University of Bristol ...

Research paper thumbnail of A soft error robust and power aware memory design

Proceedings of the 20th …, Jan 1, 2007

Research paper thumbnail of Increasing memory yield in future technologies through innovative design

Quality of Electronic …, Jan 1, 2009

Abstract Future technologies, with ever shrinking devices and higher densities, bring along highe... more Abstract Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and ...

Research paper thumbnail of Highly Reliable Power Aware Memory Design

On-Line Testing Symposium, 2007 …, Jan 1, 2007

I. I NTRODUCTION The design of low-power RAM is crucial for the semiconductor industry. Over 50 p... more I. I NTRODUCTION The design of low-power RAM is crucial for the semiconductor industry. Over 50 percent of a modern System-on-a Chip (SOC) is currently occupied by memory and the ratio is increasing. In current microprocessors, more than 30 percent of the chip area is ...

Research paper thumbnail of Improved decoding algorithm for high reliable reed muller coding

SOC Conference, 2007 IEEE …, Jan 1, 2008

Abstract A new decoding technique for triple error Reed-Muller codes is proposed. In the best of ... more Abstract A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip triple error correcting scheme is reported. We've compared the area, delay and power overhead for ...

Research paper thumbnail of Area Reliability Trade-Off in Improved Reed Muller Coding

Embedded Computer Systems: …, Jan 1, 2008

M. Berekovic, N. Dimopoulos, and S. Wong (Eds.): SAMOS 2008, LNCS 5114, pp. 116–125, 2008. © Spri... more M. Berekovic, N. Dimopoulos, and S. Wong (Eds.): SAMOS 2008, LNCS 5114, pp. 116–125, 2008. © Springer-Verlag Berlin Heidelberg 2008 ... Area Reliability Trade-Off in Improved Reed ... Costas Argyrides2, Stephania Loizidou1, and Dhiraj K. Pradhan2

Research paper thumbnail of Improved Yield in Nanotechnology Circuits Using Non-square Meshes

Proceedings of the 2010 …, Jan 1, 2010

Abstract—Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowire... more Abstract—Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected ...

Research paper thumbnail of CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

Circuits and Systems …, Jan 1, 2007

Abstract— This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high en... more Abstract— This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the ...

Research paper thumbnail of Application Specific-Area Reliability Trade-Off in Improved Reed Muller Coding

Lecture Notes in …, Jan 1, 2008

Research paper thumbnail of 26th IEEE VLSI Test Symposium (vts 2008)

For technologies beyond the 45 nm node, radiation induced transients will last longer than one cl... more For technologies beyond the 45 nm node, radiation induced transients will last longer than one clock cycle. In this scenario, temporal redundancy techniques will no longer be able to cope with radiation induced soft errors, while spatial redundancy techniques still impose high ...

Research paper thumbnail of 2008 Reviewers List

IEEE TRANSACTIONS …, Jan 1, 2009

... Daniel Brown Sharon Browning Soren Brunak Vladimir Brusic Kenneth Bryan David Bryant Jeremy B... more ... Daniel Brown Sharon Browning Soren Brunak Vladimir Brusic Kenneth Bryan David Bryant Jeremy Buhler Ralf Bundschuh Chris Bystroff ... Tony Chiang Benny Chor Ferdinando Cicalese Matteo Comin Lenore Cowen Maxime Crochemore Lisa Croner Miklos Csuros Xinping Cui ...

Research paper thumbnail of Multiple Event Upsets Aware FPGAs Using Protected Schemes

Research paper thumbnail of 2009 10th International Symposium on Quality of Electronic Design

Abstract Future technologies, with ever shrinking devices and higher densities, bring along highe... more Abstract Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and ...

Research paper thumbnail of 2010 IEEE Annual Symposium on VLSI

Abstract— Reconfigurable analog-to-digital converters (ADC) have been receiving increased attenti... more Abstract— Reconfigurable analog-to-digital converters (ADC) have been receiving increased attention in the research community for the capability to adapt to continuously varying signal processing requirements. The reconfigurable ADC is particularly advantageous in ...

Research paper thumbnail of Matrix-Based Codes for Adjacent Error Correction

Nuclear Science, …, Jan 1, 2010

Page 1. 2106 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010 Matrix-Based Codes... more Page 1. 2106 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010 Matrix-Based Codes for Adjacent Error Correction Costas A. Argyrides, Pedro Reviriego, Dhiraj K. Pradhan, and Juan Antonio Maestro ...

Research paper thumbnail of Reviewers List

Computers, IEEE …, Jan 1, 2007