DIPAK SITARAM MARATHE - Academia.edu (original) (raw)
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Papers by DIPAK SITARAM MARATHE
International Journal of Electronics and Telecommunications
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2019 International Conference on Nascent Technologies in Engineering (ICNTE), 2019
This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to ... more This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to digital converter (ADC)used in the wireless sensor node (WSN). A SAR is either synchronous or mixed mode logic, and it has a ring counter and output register. A proposed mixed mode logic is to partitioning the design into synchronous logic each having its own clock and data with asynchronous logic is exchanged asynchronously using handshake signals. This combination allows it to decrease the power and making it faster. The proposed low power SAR logic circuits are designed and simulated using TSMC 0.18 mmm CMOS technology. Synchronous and mixed mode SAR logic achieves power of 6.35 nW and 5.72 nW respectively at 1 VVV.
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Indian Journal of Science and Technology, 2016
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International Journal of Image, Graphics and Signal Processing, 2019
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International Journal of Engineering and Manufacturing, 2021
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Norchip 2012, 2012
ABSTRACT
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International Journal of Electronics and Telecommunications
Bookmarks Related papers MentionsView impact
2019 International Conference on Nascent Technologies in Engineering (ICNTE), 2019
This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to ... more This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to digital converter (ADC)used in the wireless sensor node (WSN). A SAR is either synchronous or mixed mode logic, and it has a ring counter and output register. A proposed mixed mode logic is to partitioning the design into synchronous logic each having its own clock and data with asynchronous logic is exchanged asynchronously using handshake signals. This combination allows it to decrease the power and making it faster. The proposed low power SAR logic circuits are designed and simulated using TSMC 0.18 mmm CMOS technology. Synchronous and mixed mode SAR logic achieves power of 6.35 nW and 5.72 nW respectively at 1 VVV.
Bookmarks Related papers MentionsView impact
Indian Journal of Science and Technology, 2016
Bookmarks Related papers MentionsView impact
International Journal of Image, Graphics and Signal Processing, 2019
Bookmarks Related papers MentionsView impact
International Journal of Engineering and Manufacturing, 2021
Bookmarks Related papers MentionsView impact
Norchip 2012, 2012
ABSTRACT
Bookmarks Related papers MentionsView impact