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Papers by DIPAK SITARAM MARATHE

Research paper thumbnail of A Systematic Approach to Determining the Duty Cycle for Regenerative Comparator Used in WSN

International Journal of Electronics and Telecommunications

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Research paper thumbnail of A 10-Bit 10-Ms/S 5.72 nW Mixed SAR Logic for ADC Used in Wireless Sensor Node

2019 International Conference on Nascent Technologies in Engineering (ICNTE), 2019

This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to ... more This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to digital converter (ADC)used in the wireless sensor node (WSN). A SAR is either synchronous or mixed mode logic, and it has a ring counter and output register. A proposed mixed mode logic is to partitioning the design into synchronous logic each having its own clock and data with asynchronous logic is exchanged asynchronously using handshake signals. This combination allows it to decrease the power and making it faster. The proposed low power SAR logic circuits are designed and simulated using TSMC 0.18 mmm CMOS technology. Synchronous and mixed mode SAR logic achieves power of 6.35 nW and 5.72 nW respectively at 1 VVV.

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Research paper thumbnail of An Optimized Successive Approximation Register used in ADC for Wireless Sensor Nodes

Indian Journal of Science and Technology, 2016

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Research paper thumbnail of A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

International Journal of Image, Graphics and Signal Processing, 2019

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Research paper thumbnail of COVID-19 Patient Health Monitoring System

International Journal of Engineering and Manufacturing, 2021

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Research paper thumbnail of A survey on mixed operating mode/self synchronization

Norchip 2012, 2012

ABSTRACT

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Research paper thumbnail of A Systematic Approach to Determining the Duty Cycle for Regenerative Comparator Used in WSN

International Journal of Electronics and Telecommunications

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A 10-Bit 10-Ms/S 5.72 nW Mixed SAR Logic for ADC Used in Wireless Sensor Node

2019 International Conference on Nascent Technologies in Engineering (ICNTE), 2019

This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to ... more This paper proposes a 10-bit successive approximation register (SAR) digital logic for analog to digital converter (ADC)used in the wireless sensor node (WSN). A SAR is either synchronous or mixed mode logic, and it has a ring counter and output register. A proposed mixed mode logic is to partitioning the design into synchronous logic each having its own clock and data with asynchronous logic is exchanged asynchronously using handshake signals. This combination allows it to decrease the power and making it faster. The proposed low power SAR logic circuits are designed and simulated using TSMC 0.18 mmm CMOS technology. Synchronous and mixed mode SAR logic achieves power of 6.35 nW and 5.72 nW respectively at 1 VVV.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of An Optimized Successive Approximation Register used in ADC for Wireless Sensor Nodes

Indian Journal of Science and Technology, 2016

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

International Journal of Image, Graphics and Signal Processing, 2019

Bookmarks Related papers MentionsView impact

Research paper thumbnail of COVID-19 Patient Health Monitoring System

International Journal of Engineering and Manufacturing, 2021

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A survey on mixed operating mode/self synchronization

Norchip 2012, 2012

ABSTRACT

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