Dan Poznanovic - Academia.edu (original) (raw)

Papers by Dan Poznanovic

Research paper thumbnail of The SRC-6E Reconfigurable Computing Environment

In this paper, we overview general hardware architecture and a programming model of SRC-6E TM rec... more In this paper, we overview general hardware architecture and a programming model of SRC-6E TM reconfigurable computers, and compare the performance of the SRC-6E machine vs. Intel ® Pentium IV TM. SRC-6E execution time measurements have been performed using three different approaches. In the first approach, the entire end-to-end execution time is taken into account. In the second approach, the configuration time of FPGAs have been omitted. In the third approach both configuration and data transfer overheads have been omitted. All measurements have been done for different numbers of data blocks. The results show that the SRC-6E can outperform a general-purpose microprocessor for computationally intensive algorithms by a factor of over 1500. However, overhead due to configuration and data transfer must be properly dealt with by the application or the system’s run-time environment to achieve the full throughput potential. Some techniques are suggested to minimize the influence of the c...

Research paper thumbnail of Application defined processors

Linux Journal, 2005

A foldable, portable bicycle in which the handlebar, its elongated post, the seat assembly, the p... more A foldable, portable bicycle in which the handlebar, its elongated post, the seat assembly, the pedal crank and the frame are foldable quickly and easily into a compact and regular-shaped package that is easily portable and storable, and are unfoldable with similar speed and ease into a safe, durable and comfortable bicycle that accommodates adults of normal size. The frame is designed with a low profile that is substantially the same in height and thickness as the dimensions of the wheels and their supports, and the handlebar and seat assemblies extend upwardly to normal height, but fold and collapse, along with the pedals, to substantially within the confines outlined by the folded frame. Quick release latches are provided for the handlebar post, the seat post sections, the frame hinge and the pedal hinges, and the pedal cranks are designed for effective performance and easy, compact folding. Optional features include an enclosed front carrying compartment, a bracing cable permitting the seat post to be made of lighter materials, a rear carrying rack that extends the flat and low profile across the rear frame section, and a shopping cart mode in which the partially folded frame is held with the two bicycle wheels parallel, and an auxiliary wheel assembly stored in the mid-portion of the frame is swung out to form a 3-wheel cart with a carrying deck.

Research paper thumbnail of Is high-performance reconfigurable computing the next supercomputing paradigm?

Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC'06, 2006

Research paper thumbnail of Performance and overhead in a hybrid reconfigurable computer

Proceedings International Parallel and Distributed Processing Symposium

Research paper thumbnail of OpenFPGA CoreLib core library interoperability effort

Research paper thumbnail of The SRC-6E Reconfigurable Computing Environment

In this paper, we overview general hardware architecture and a programming model of SRC-6E TM rec... more In this paper, we overview general hardware architecture and a programming model of SRC-6E TM reconfigurable computers, and compare the performance of the SRC-6E machine vs. Intel ® Pentium IV TM. SRC-6E execution time measurements have been performed using three different approaches. In the first approach, the entire end-to-end execution time is taken into account. In the second approach, the configuration time of FPGAs have been omitted. In the third approach both configuration and data transfer overheads have been omitted. All measurements have been done for different numbers of data blocks. The results show that the SRC-6E can outperform a general-purpose microprocessor for computationally intensive algorithms by a factor of over 1500. However, overhead due to configuration and data transfer must be properly dealt with by the application or the system’s run-time environment to achieve the full throughput potential. Some techniques are suggested to minimize the influence of the c...

Research paper thumbnail of Application defined processors

Linux Journal, 2005

A foldable, portable bicycle in which the handlebar, its elongated post, the seat assembly, the p... more A foldable, portable bicycle in which the handlebar, its elongated post, the seat assembly, the pedal crank and the frame are foldable quickly and easily into a compact and regular-shaped package that is easily portable and storable, and are unfoldable with similar speed and ease into a safe, durable and comfortable bicycle that accommodates adults of normal size. The frame is designed with a low profile that is substantially the same in height and thickness as the dimensions of the wheels and their supports, and the handlebar and seat assemblies extend upwardly to normal height, but fold and collapse, along with the pedals, to substantially within the confines outlined by the folded frame. Quick release latches are provided for the handlebar post, the seat post sections, the frame hinge and the pedal hinges, and the pedal cranks are designed for effective performance and easy, compact folding. Optional features include an enclosed front carrying compartment, a bracing cable permitting the seat post to be made of lighter materials, a rear carrying rack that extends the flat and low profile across the rear frame section, and a shopping cart mode in which the partially folded frame is held with the two bicycle wheels parallel, and an auxiliary wheel assembly stored in the mid-portion of the frame is swung out to form a 3-wheel cart with a carrying deck.

Research paper thumbnail of Is high-performance reconfigurable computing the next supercomputing paradigm?

Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC'06, 2006

Research paper thumbnail of Performance and overhead in a hybrid reconfigurable computer

Proceedings International Parallel and Distributed Processing Symposium

Research paper thumbnail of OpenFPGA CoreLib core library interoperability effort