Daniel Yohannes - Academia.edu (original) (raw)

Papers by Daniel Yohannes

Bulletin of the American Physical Society, 2019

Scientific Reports, 2020

One of the most challenging obstacles to realizing exascale computing is minimizing the energy co... more One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology’s lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10−6, and a 4 × 4 array can be fully addressed with bit select error rates of 10−6. This d...

Ieee Transactions on Applied Superconductivity, 2007

2013 IEEE 14th International Superconductive Electronics Conference (ISEC), 2013

ABSTRACT

IEEE Transactions on Applied Superconductivity, 2015

We report on technique and results for superconductor electronics fabrication process, featuring ... more We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of Aluminum as an etch stop in the metalvia stack. The drawback of the previous approach was the difficulty in processing Aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm 2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

IEEE Transactions on Applied Superconductivity, 2015

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resis... more We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Superconductor Science and Technology, 2007

It has been found that the critical current of Josephson junctions in superconducting integrated ... more It has been found that the critical current of Josephson junctions in superconducting integrated circuits may depend on the environment surrounding the junctions and on how a particular junction is connected (wired) to other junctions and circuit elements. This may cause large, pattern-dependent deviations of the junctions' critical currents from design values and ultimately limit the yield and performance of superconducting digital integrated circuits. In particular, we have found a difference in the critical current of grounded and floating junctions, and a dependence of the critical current on the size of metal structures connected to the junction-the 'antenna' effect. Experimental data were obtained for Nb/AlO x /Nb Josephson junctions fabricated on 150 mm wafers by an 11-layer process for superconducting integrated circuits. The results are explained by plasma process-induced damage to ultra-thin tunnel barriers. The most damaging plasma processing fabrication steps are discussed.

IEEE Transactions on Appiled Superconductivity, 2005

We have developed and experimentally demonstrated several new RSFQ circuits, designed as componen... more We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of 512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.

IEEE Transactions on Appiled Superconductivity, 2003

Our Nb/AlO /Nb planarized process has been upgraded by adding extra dielectric and Nb wiring laye... more Our Nb/AlO /Nb planarized process has been upgraded by adding extra dielectric and Nb wiring layers and the installation of an Inductively Coupled Plasma (ICP) etcher. Much higher quartz etch rates as well as reduced residue are achieved with ICP etch. Etch uniformities of both Nb and quartz are also improved significantly. Damage to Nb during the fabrication process has been investigated. We have found that dry etching in SF 6 plasma has a significant effect on the quality of Nb films under certain conditions with damage coinciding with the presence of in situ deposited Al.

IEEE Transactions on Applied Superconductivity, 2013

Many applications of Nb/Al-AlO_x/Nb Josephson junctions (JJs) in supercondu... more Many applications of Nb/Al-AlO_x/Nb Josephson junctions (JJs) in superconducting electronics require high-quality tunnel barriers with low subgap leakage that is usually characterized by figure of merit V_m = I_c R_sg, where I_c is the critical current and R_sg is the subgap resistance at 2 mV and 4.2 K. It is widely believed, and there is considerable literature suggesting, that quality and reproducibility of JJs critically depend on the intrinsic stress in Nb/Al-AlO_x/Nb trilayers, and the stress therefore should be carefully minimized and controlled. Contrary to this belief, we show that JJ quality V_m and reproducibility do not depend on the stress in the trilayer, at least in the studied range from -300 to 300 MPa. In this range, V_m depends neither on the stress in a Nb/Al base electrode nor in a Nb counter electrode. We have found, however, that V_m crucially depends on the way the tunnel barrier formation by thermal oxidation of Al is done. For instance, room-temperature dynamic oxidation (in O₂ flow at low pressures) in a cryopumped chamber leads to poor run-to-run reproducibility of V_m and reduced V_m values, whereas dynamic oxidation at the same parameters but in a chamber with a turbomolecular pump results in high V_m values and excellent run-to-run reproducibility.

IEEE Transactions on Applied Superconductivity, 2009

It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayer... more It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayered structures such as superconductor integrated circuits depends on the junction environment and on which wiring layers make contacts to the junction electrodes, and at which stage of the fabrication process. In particular, it is shown that contact holes between the junction base electrode layer and

IEEE Transactions on Applied Superconductivity, 2009

... ACKNOWLEDGMENT The authors thank Rick Hunt and John Vivalda for their in-valuable contributio... more ... ACKNOWLEDGMENT The authors thank Rick Hunt and John Vivalda for their in-valuable contribution in fabricating the wafers, Saad Sarwana for collaborating in testing some of the implemented circuits, Alex Kirichenko for designing the second ... [1] IV Vernik, DE Kirichenko ...

IEEE Transactions on Applied Superconductivity, 2007

Results of the development of an advanced fabrication process for superconductor integrated circu... more Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA cm 2 Nb AlO x Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoN x resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 m; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of Rapid Single Flux Quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of 13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

IEEE Transactions on Applied Superconductivity, 2007

A set of diagnostic chips for process control and design parameters evaluation has been developed... more A set of diagnostic chips for process control and design parameters evaluation has been developed for HYPRES' 1.0kA cm 2 , 4.5 kA cm 2 , and 20 kA cm 2 fabrication processes, consisting of four 5 5-mm chips. Testing was performed on automated test setup (OCTOPUX) that automatically logs results and maintains records of fabrication process and design parameters. The design of diagnostic structures and automated testing algorithms are discussed. Statistical data are presented on the uniformity and run-to-run variation of the critical currents, critical current density, junction size, inductances, and other fabrication and design parameters collected since September 2005. The influence of the fabrication parameters deviation on operational margins and yield of large superconducting digital integrated circuits is discussed, as well as requirements for the 20kA cm 2 (80 GHz) process.

IEEE Transactions on Applied Superconductivity, 2011

New technology for superconductor integrated circuits has been developed and is presented. It emp... more New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (I c) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in I c and tunneling characteristics of Nb/Al/AlO x /Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (J c) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such J c variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlO x tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of J c. At least two DSLs are required to completely protect JJs from impurity diffusion effects-right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from ~3 nm to~ 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlO x /Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of J c uniformity on 150-mm wafer has also been obtained along with large improvements in J c targeting and run-to-run reproducibility.

IEEE Transactions on Appiled Superconductivity, 2005

HYPRES has developed new fabrication processes for higher critical current density Josephson junc... more HYPRES has developed new fabrication processes for higher critical current density Josephson junctions (JJ's). These processes incorporate an additional anodization step for junction insulation, which enables fabrication of junctions down to submicron sizes. A set of new processing tools has been employed, including a high density (ICP) plasma etching of niobium and aluminum, and low temperature plasma-enhanced chemical vapor deposition of interlayer dielectric (SiO 2) from a TEOS source. A set of new parametric control monitor (PCM) test chips has been designed and implemented. Results of electric and SEM characterization of JJ's, wiring, and contact-hole etching are presented. The critical current spreads and shunt resistance uniformity along with the effects of junction shape are discussed. The critical current 1 spreads of 1.2% have been achieved for the 4.5 kA cm 2 process.

Ieee Transactions on Applied Superconductivity, 2009

Bulletin of the American Physical Society, 2019

Scientific Reports, 2020

One of the most challenging obstacles to realizing exascale computing is minimizing the energy co... more One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology’s lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10−6, and a 4 × 4 array can be fully addressed with bit select error rates of 10−6. This d...

Ieee Transactions on Applied Superconductivity, 2007

2013 IEEE 14th International Superconductive Electronics Conference (ISEC), 2013

ABSTRACT

IEEE Transactions on Applied Superconductivity, 2015

We report on technique and results for superconductor electronics fabrication process, featuring ... more We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of Aluminum as an etch stop in the metalvia stack. The drawback of the previous approach was the difficulty in processing Aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm 2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

IEEE Transactions on Applied Superconductivity, 2015

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resis... more We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Superconductor Science and Technology, 2007

It has been found that the critical current of Josephson junctions in superconducting integrated ... more It has been found that the critical current of Josephson junctions in superconducting integrated circuits may depend on the environment surrounding the junctions and on how a particular junction is connected (wired) to other junctions and circuit elements. This may cause large, pattern-dependent deviations of the junctions' critical currents from design values and ultimately limit the yield and performance of superconducting digital integrated circuits. In particular, we have found a difference in the critical current of grounded and floating junctions, and a dependence of the critical current on the size of metal structures connected to the junction-the 'antenna' effect. Experimental data were obtained for Nb/AlO x /Nb Josephson junctions fabricated on 150 mm wafers by an 11-layer process for superconducting integrated circuits. The results are explained by plasma process-induced damage to ultra-thin tunnel barriers. The most damaging plasma processing fabrication steps are discussed.

IEEE Transactions on Appiled Superconductivity, 2005

We have developed and experimentally demonstrated several new RSFQ circuits, designed as componen... more We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of 512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.

IEEE Transactions on Appiled Superconductivity, 2003

Our Nb/AlO /Nb planarized process has been upgraded by adding extra dielectric and Nb wiring laye... more Our Nb/AlO /Nb planarized process has been upgraded by adding extra dielectric and Nb wiring layers and the installation of an Inductively Coupled Plasma (ICP) etcher. Much higher quartz etch rates as well as reduced residue are achieved with ICP etch. Etch uniformities of both Nb and quartz are also improved significantly. Damage to Nb during the fabrication process has been investigated. We have found that dry etching in SF 6 plasma has a significant effect on the quality of Nb films under certain conditions with damage coinciding with the presence of in situ deposited Al.

IEEE Transactions on Applied Superconductivity, 2013

Many applications of Nb/Al-AlO_x/Nb Josephson junctions (JJs) in supercondu... more Many applications of Nb/Al-AlO_x/Nb Josephson junctions (JJs) in superconducting electronics require high-quality tunnel barriers with low subgap leakage that is usually characterized by figure of merit V_m = I_c R_sg, where I_c is the critical current and R_sg is the subgap resistance at 2 mV and 4.2 K. It is widely believed, and there is considerable literature suggesting, that quality and reproducibility of JJs critically depend on the intrinsic stress in Nb/Al-AlO_x/Nb trilayers, and the stress therefore should be carefully minimized and controlled. Contrary to this belief, we show that JJ quality V_m and reproducibility do not depend on the stress in the trilayer, at least in the studied range from -300 to 300 MPa. In this range, V_m depends neither on the stress in a Nb/Al base electrode nor in a Nb counter electrode. We have found, however, that V_m crucially depends on the way the tunnel barrier formation by thermal oxidation of Al is done. For instance, room-temperature dynamic oxidation (in O₂ flow at low pressures) in a cryopumped chamber leads to poor run-to-run reproducibility of V_m and reduced V_m values, whereas dynamic oxidation at the same parameters but in a chamber with a turbomolecular pump results in high V_m values and excellent run-to-run reproducibility.

IEEE Transactions on Applied Superconductivity, 2009

It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayer... more It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayered structures such as superconductor integrated circuits depends on the junction environment and on which wiring layers make contacts to the junction electrodes, and at which stage of the fabrication process. In particular, it is shown that contact holes between the junction base electrode layer and

IEEE Transactions on Applied Superconductivity, 2009

... ACKNOWLEDGMENT The authors thank Rick Hunt and John Vivalda for their in-valuable contributio... more ... ACKNOWLEDGMENT The authors thank Rick Hunt and John Vivalda for their in-valuable contribution in fabricating the wafers, Saad Sarwana for collaborating in testing some of the implemented circuits, Alex Kirichenko for designing the second ... [1] IV Vernik, DE Kirichenko ...

IEEE Transactions on Applied Superconductivity, 2007

Results of the development of an advanced fabrication process for superconductor integrated circu... more Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA cm 2 Nb AlO x Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoN x resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 m; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of Rapid Single Flux Quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of 13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

IEEE Transactions on Applied Superconductivity, 2007

A set of diagnostic chips for process control and design parameters evaluation has been developed... more A set of diagnostic chips for process control and design parameters evaluation has been developed for HYPRES' 1.0kA cm 2 , 4.5 kA cm 2 , and 20 kA cm 2 fabrication processes, consisting of four 5 5-mm chips. Testing was performed on automated test setup (OCTOPUX) that automatically logs results and maintains records of fabrication process and design parameters. The design of diagnostic structures and automated testing algorithms are discussed. Statistical data are presented on the uniformity and run-to-run variation of the critical currents, critical current density, junction size, inductances, and other fabrication and design parameters collected since September 2005. The influence of the fabrication parameters deviation on operational margins and yield of large superconducting digital integrated circuits is discussed, as well as requirements for the 20kA cm 2 (80 GHz) process.

IEEE Transactions on Applied Superconductivity, 2011

New technology for superconductor integrated circuits has been developed and is presented. It emp... more New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (I c) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in I c and tunneling characteristics of Nb/Al/AlO x /Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (J c) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such J c variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlO x tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of J c. At least two DSLs are required to completely protect JJs from impurity diffusion effects-right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from ~3 nm to~ 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlO x /Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of J c uniformity on 150-mm wafer has also been obtained along with large improvements in J c targeting and run-to-run reproducibility.

IEEE Transactions on Appiled Superconductivity, 2005

HYPRES has developed new fabrication processes for higher critical current density Josephson junc... more HYPRES has developed new fabrication processes for higher critical current density Josephson junctions (JJ's). These processes incorporate an additional anodization step for junction insulation, which enables fabrication of junctions down to submicron sizes. A set of new processing tools has been employed, including a high density (ICP) plasma etching of niobium and aluminum, and low temperature plasma-enhanced chemical vapor deposition of interlayer dielectric (SiO 2) from a TEOS source. A set of new parametric control monitor (PCM) test chips has been designed and implemented. Results of electric and SEM characterization of JJ's, wiring, and contact-hole etching are presented. The critical current spreads and shunt resistance uniformity along with the effects of junction shape are discussed. The critical current 1 spreads of 1.2% have been achieved for the 4.5 kA cm 2 process.

Ieee Transactions on Applied Superconductivity, 2009